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5497FMQB PDF预览

5497FMQB

更新时间: 2024-01-24 04:53:19
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
8页 152K
描述
Synchronous Modulo-64 Bit Rate Multiplier

5497FMQB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer零件包装代码:DFP
包装说明:CERAMIC, DFP-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.72Is Samacsys:N
其他特性:BINARY RATE MULTIPLIER; ENABLE INPUT AND OUTPUTS; COMPLEMENTARY OUTPUTS计数方向:UP
系列:TTL/H/LJESD-30 代码:R-GDFP-F16
JESD-609代码:e0长度:9.6645 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS位数:6
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):39 ns
认证状态:Not Qualified座面最大高度:2.032 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:TIN LEAD端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.604 mm最小 fmax:25 MHz
Base Number Matches:1

5497FMQB 数据手册

 浏览型号5497FMQB的Datasheet PDF文件第2页浏览型号5497FMQB的Datasheet PDF文件第3页浏览型号5497FMQB的Datasheet PDF文件第4页浏览型号5497FMQB的Datasheet PDF文件第5页浏览型号5497FMQB的Datasheet PDF文件第6页浏览型号5497FMQB的Datasheet PDF文件第7页 
June 1989  
5497/DM7497  
Synchronous Modulo-64 Bit Rate Multiplier  
General Description  
The ’97 contains a synchronous 6-stage binary counter and  
six decoding gates that serve to gate the clock through to  
the output at a sub-multiple of the input frequency. The out-  
put pulse rate, relative to the clock frequency, is determined  
by signals applied to the Select (S0S5) inputs. Both true  
and complement outputs are available, along with an enable  
input for each. A Count Enable input and a Terminal Count  
output are provided for cascading two or more packages.  
An asynchronous Master Reset input prevents counting and  
resets the counter.  
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/9780–2  
e
e
V
Pin 16  
CC  
GND  
TL/F/9780–1  
Pin 8  
Order Number 5497DMQB, 5497FMQB or DM7497N  
See NS Package Number J16A, N16E or W16A  
Pin Names  
Description  
S0S5  
Rate Select Inputs  
E
E
O
O
Enable Input (Active LOW)  
Z
Z
Y
Enable Input  
Y
CE  
CP  
MR  
Count Enable Input (Active LOW)  
Clock Pulse Input (Active Rising Edge)  
Asynchronous Master Reset Input (Active HIGH)  
Gated Clock Output (Active LOW)  
O
O
Z
Complement Output (Active HIGH)  
y
TC  
Terminal Count Output (Active LOW)  
C
1995 National Semiconductor Corporation  
TL/F/9780  
RRD-B30M115/Printed in U. S. A.  

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