5497DMQB

更新时间： 2024-02-29 08:21:20

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器逻辑集成电路输出元件输入元件
页数	文件大小	规格书
8页	152K
描述
Synchronous Modulo-64 Bit Rate Multiplier

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数据手册

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5497DMQB 数据手册

June 1989

5497/DM7497

Synchronous Modulo-64 Bit Rate Multiplier

General Description

The ’97 contains a synchronous 6-stage binary counter and

six decoding gates that serve to gate the clock through to

the output at a sub-multiple of the input frequency. The out-

put pulse rate, relative to the clock frequency, is determined

by signals applied to the Select (S0–S5) inputs. Both true

and complement outputs are available, along with an enable

input for each. A Count Enable input and a Terminal Count

output are provided for cascading two or more packages.

An asynchronous Master Reset input prevents counting and

resets the counter.

Connection Diagram

Logic Symbol

Dual-In-Line Package

TL/F/9780–2

Pin 16

GND

TL/F/9780–1

Pin 8

Order Number 5497DMQB, 5497FMQB or DM7497N

See NS Package Number J16A, N16E or W16A

Pin Names

Description

S0–S5

Rate Select Inputs

Enable Input (Active LOW)

Enable Input

Count Enable Input (Active LOW)

Clock Pulse Input (Active Rising Edge)

Asynchronous Master Reset Input (Active HIGH)

Gated Clock Output (Active LOW)

Complement Output (Active HIGH)

Terminal Count Output (Active LOW)

1995 National Semiconductor Corporation

TL/F/9780

RRD-B30M115/Printed in U. S. A.

12 3 4 5 6 7 8

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