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5474DMQB PDF预览

5474DMQB

更新时间: 2024-01-21 19:13:50
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器锁存器逻辑集成电路
页数 文件大小 规格书
6页 124K
描述
Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

5474DMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.47系列:TTL/H/L
JESD-30 代码:R-GDFP-F14JESD-609代码:e0
负载电容(CL):15 pF逻辑集成电路类型:D FLIP-FLOP
最大I(ol):0.016 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL14,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):30 mA传播延迟(tpd):40 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:2.032 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.2865 mm最小 fmax:15 MHz

5474DMQB 数据手册

 浏览型号5474DMQB的Datasheet PDF文件第2页浏览型号5474DMQB的Datasheet PDF文件第3页浏览型号5474DMQB的Datasheet PDF文件第4页浏览型号5474DMQB的Datasheet PDF文件第5页浏览型号5474DMQB的Datasheet PDF文件第6页 
June 1989  
5474/DM5474/DM7474  
Dual Positive-Edge-Triggered D Flip-Flops  
with Preset, Clear and Complementary Outputs  
General Description  
This device contains two independent positive-edge-trig-  
gered D flip-flops with complementary outputs. The informa-  
tion on the D input is accepted by the flip-flops on the posi-  
tive going edge of the clock pulse. The triggering occurs at a  
voltage level and is not directly related to the transition time  
of the rising edge of the clock. The data on the D input may  
be changed while the clock is low or high without affecting  
the outputs as long as the data setup and hold times are not  
violated. A low logic level on the preset or clear inputs will  
set or reset the outputs regardless of the logic levels of the  
other inputs.  
Features  
Y
Alternate Military/Aerospace device (5474) is available.  
Contact a National Semiconductor Sales Office/Distrib-  
utor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6526–1  
Order Number 5474DMQB, 5474FMQB, DM5474J, DM5474W, DM7474M or DM7474N  
See NS Package Number J14A, M14A, N14A or W14B  
Function Table  
Inputs  
CLR  
Outputs  
PR  
CLK  
D
Q
Q
L
H
L
H
L
X
X
X
X
X
H
L
H
L
L
H
L
X
H*  
H
H*  
L
H
H
H
H
H
H
u
u
L
L
H
X
Q
0
Q
0
e
e
e
H
X
L
High Logic Level  
Either Low or High Logic Level  
Low Logic Level  
e
e
Positive-going transition of the clock.  
This configuration is nonstable; that is, it will not persist when either the preset and/or clear  
inputs return to their inactive (high) level.  
u
*
e
Q
0
The output logic level of Q before the indicated input conditions were established.  
C
1995 National Semiconductor Corporation  
TL/F/6526  
RRD-B30M105/Printed in U. S. A.  

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