5秒后页面跳转
54191FMQB PDF预览

54191FMQB

更新时间: 2024-01-07 00:39:35
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
6页 132K
描述
Synchronous Up/Down 4-Bit Binary Counter with Mode Control

54191FMQB 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.77
逻辑集成电路类型:DECADE COUNTERBase Number Matches:1

54191FMQB 数据手册

 浏览型号54191FMQB的Datasheet PDF文件第2页浏览型号54191FMQB的Datasheet PDF文件第3页浏览型号54191FMQB的Datasheet PDF文件第4页浏览型号54191FMQB的Datasheet PDF文件第5页浏览型号54191FMQB的Datasheet PDF文件第6页 
June 1989  
54191/DM54191/DM74191 Synchronous Up/Down  
4-Bit Binary Counter with Mode Control  
General Description  
This circuit is a synchronous, reversible, up/down counter.  
The 191 is a 4-bit binary counter. Synchronous operation is  
provided by having all flip-flops clocked simultaneously so  
that the outputs change simultaneously when so instructed  
by the steering logic. This mode of operation eliminates the  
output counting spikes normally associated with asynchro-  
nous (ripple clock) counters.  
Two outputs have been made available to perform the cas-  
cading function: ripple clock and maximum/minimum count.  
The latter output produces a high-level output pulse with a  
duration approximately equal to one complete cycle of the  
clock when the counter overflows or underflows. The ripple  
clock output produces a low-level output pulse equal in  
width to the low-level portion of the clock input when an  
overflow or underflow condition exists. The counters can be  
easily cascaded by feeding the ripple clock output to the  
enable input of the succeeding counter if parallel clocking is  
used, or to the clock input if parallel enabling is used. The  
maximum/minimum count output can be used to accom-  
plish look-ahead for high-speed operation.  
The outputs of the four master-slave flip-flops are triggered  
on a low-to-high level transition of the clock input, if the  
enable input is low. A high at the enable input inhibits count-  
ing. Level changes at either the enable input or the down/  
up input should be made only when the clock input is high.  
The direction of the count is determined by the level of the  
down/up input. When low, the counter counts up and when  
high, it counts down.  
Features  
Y
Single down/up count control line  
This counter is fully programmable; that is, the outputs may  
be preset to either level by placing a low on the load input  
and entering the desired data at the data inputs. The output  
will change independent of the level of the clock input. This  
feature allows the counters to be used as modulo-N dividers  
by simply modifying the count length with the preset inputs.  
Y
Count enable control input  
Y
Ripple clock output for cascading  
Y
Asynchronously presettable with load control  
Y
Parallel outputs  
Y
Cascadable for n-bit applications  
The clock, down/up, and load inputs are buffered to lower  
the drive requirement; which significantly reduces the num-  
ber of clock drivers, etc., required for long parallel words.  
Y
Alternate Military/Aerospace device (54191) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6562–1  
Order Number 54191DMQB, 54191FMQB,  
DM54191J, DM54191W or DM74191N  
See NS Package Number J16A, N16E or W16A  
C
1995 National Semiconductor Corporation  
TL/F/6562  
RRD-B30M105/Printed in U. S. A.  

与54191FMQB相关器件

型号 品牌 描述 获取价格 数据表
54191J/B ROCHESTER Decade Counter,

获取价格

54191W/B ROCHESTER Decade Counter,

获取价格

54192 TI Counter

获取价格

54192-2274 MOLEX Board Connector, 110+110 Contact(s), 2+2 Row(s), Female, Straight, 0.025 inch Pitch, Surfa

获取价格

5419-24-0 POMONA Interconnection Device

获取价格

5419-24-2 POMONA Interconnection Device

获取价格