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54173

更新时间: 2024-01-23 16:09:33
品牌 Logo 应用领域
美国国家半导体 - NSC 端子和端子排
页数 文件大小 规格书
6页 134K
描述
TRI-STATE Quad Registers

54173 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.75
终端性别:FEMALE端子和端子排类型:RING TERMINAL
线规:250 AWGBase Number Matches:1

54173 数据手册

 浏览型号54173的Datasheet PDF文件第2页浏览型号54173的Datasheet PDF文件第3页浏览型号54173的Datasheet PDF文件第4页浏览型号54173的Datasheet PDF文件第5页浏览型号54173的Datasheet PDF文件第6页 
June 1989  
54173/DM54173/DM74173  
TRI-STATE Quad D Registers  
É
General Description  
These four-bit registers contain D-type flip-flops with totem-  
pole TRI-STATE outputs, capable of driving highly capaci-  
tive or low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these flip-flops with  
the capability of driving the bus lines in a bus-organized sys-  
tem without need for interface or pull-up components.  
To minimize the possibility that two outputs will attempt to  
take a common bus to opposite logic levels, the output con-  
trol circuitry is designed so that the average output disable  
times are shorter than the average output enable times.  
Features  
Y
Gated enable inputs are provided for controlling the entry of  
data into the flip-flops. When both data-enable inputs are  
low, data at the D inputs are loaded into their respective flip-  
flops on the next positive transition of the buffered clock  
input. Gate output control inputs are also provided. When  
both are low, the normal logic states of the four outputs are  
available for driving the loads or bus lines. The outputs are  
disabled independently from the level of the clock by a high  
logic level at either output control input. The outputs then  
present a high impedance and neither load nor drive the bus  
line. Detailed operation is given in the function table.  
TRI-STATE outputs interface directly with system bus  
Y
Gated output control lines for enabling or disabling the  
outputs  
Y
Fully independent clock elminates restrictions for oper-  
ating in one of two modes:  
Parallel load  
Do nothing (hold)  
Y
For application as bus buffer registers  
Y
Typical propagation delay 18 ns  
Y
Typical frequency 30 MHz  
Y
Typical power dissipation 250 mW  
Y
Alternate Military/Aerospace device (54173) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Connection Diagram  
Function Table  
Dual-In-Line Package  
Inputs  
Data Enable  
Output  
Data  
D
Q
Clear Clock  
G1  
G2  
H
L
L
L
L
L
X
X
X
H
X
L
X
X
X
H
L
X
X
X
X
L
L
L
Q
0
0
0
Q
Q
u
u
u
u
L
L
L
H
H
When either M or N (or both) is (are) high the output is disabled to the  
high-impedance state; however, sequential operation of the flip-flops is  
not affected.  
e
H
high level (steady state)  
low level (steady state)  
e
L
e
low-to-high level transition  
u
X
e
don’t care (any input including transitions)  
e
established  
Q
0
the level of Q before the indicated steady state input conditions were  
TL/F/6556–1  
Order Number 54173DMQB, 54173FMQB,  
DM54173J, DM54173W or DM74173N  
See NS Package Number J16A, N16E or W16A  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6556  
RRD-B30M105/Printed in U. S. A.  

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