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4027

更新时间: 2024-02-03 08:11:44
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 128K
描述
Dual J-K Master/Slave Flip-Flop with Set and Reset

4027 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete包装说明:DIP, DIP16,.3
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57Is Samacsys:N
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
逻辑集成电路类型:J-K FLIP-FLOP湿度敏感等级:2A
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):250
电源:5/15 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B子类别:FF/Latches
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:MASTER-SLAVEBase Number Matches:1

4027 数据手册

 浏览型号4027的Datasheet PDF文件第2页浏览型号4027的Datasheet PDF文件第3页浏览型号4027的Datasheet PDF文件第4页浏览型号4027的Datasheet PDF文件第5页浏览型号4027的Datasheet PDF文件第6页 
February 1988  
CD4027BM/CD4027BC Dual J-K Master/Slave  
Flip-Flop with Set and Reset  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
These dual J-K flip-flops are monolithic complementary  
MOS (CMOS) integrated circuits constructed with N- and P-  
channel enhancement mode transistors. Each flip-flop has  
independent J, K, set, reset, and clock inputs and buffered  
Q and Q outputs. These flip-flops are edge sensitive to the  
clock input and change state on the positive-going transition  
of the clock pulses. Set or reset is independent of the clock  
and is accomplished by a high level on the respective input.  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
50 nW (typ.)  
Y
Low power  
Y
Medium speed operation  
12 MHz (typ.)  
with 10V supply  
All inputs are protected against damage due to static dis-  
.
SS  
charge by diode clamps to V  
and V  
DD  
Schematic and Connection Diagrams  
TL/F/5958–1  
Dual-In-Line Package  
Order Number CD4027B  
TL/F/5958–2  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/5958  
RRD-B30M105/Printed in U. S. A.  

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