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100355FCQR PDF预览

100355FCQR

更新时间: 2024-02-08 15:31:18
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器锁存器
页数 文件大小 规格书
10页 152K
描述
IC 100K SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CQFP24, CERPACK-24, FF/Latch

100355FCQR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QFF, QFL24,.4SQReach Compliance Code:unknown
风险等级:5.84Is Samacsys:N
JESD-30 代码:S-XQFP-F24JESD-609代码:e0
逻辑集成电路类型:MULTIPLEXER功能数量:4
输入次数:2端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:QFF
封装等效代码:QFL24,.4SQ封装形状:SQUARE
封装形式:FLATPACK电源:-4.5 V
最大电源电流(ICC):95 mAProp。Delay @ Nom-Sup:2.6 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:Multiplexer/Demultiplexers表面贴装:YES
技术:ECL100K温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

100355FCQR 数据手册

 浏览型号100355FCQR的Datasheet PDF文件第2页浏览型号100355FCQR的Datasheet PDF文件第3页浏览型号100355FCQR的Datasheet PDF文件第4页浏览型号100355FCQR的Datasheet PDF文件第5页浏览型号100355FCQR的Datasheet PDF文件第6页浏览型号100355FCQR的Datasheet PDF文件第7页 
August 1998  
100355  
Low Power Quad Multiplexer/Latch  
puts. A HIGH signal on the Master Reset (MR) input over-  
rides all the other inputs and forces the Q outputs LOW. All  
inputs have 50 kpulldown resistors.  
General Description  
The 100355 contains four transparent latches, each of which  
can accept and store data from two sources. When both En-  
able (En) inputs are LOW, the data that appears at an output  
is controlled by the Select (Sn) inputs, as shown in the Oper-  
ating Mode table. In addition to routing data from either D0 or  
D1, the Select inputs can force the outputs LOW for the case  
where the latch is transparent (both Enables are LOW) and  
can steer a HIGH signal from either D0 or D1 to an output.  
The Select inputs can be tied together for applications re-  
quiring only that data be steered from either D0 or D1. A  
positive-going signal on either Enable input latches the out-  
Features  
n Greater than 40% power reduction of the 100155  
n 2000V ESD protection  
n Pin/function compatible with 100155  
=
n Voltage compensated operating range −4.2V to −5.7V  
n Standard Microcircuit Drawing  
(SMD) 5962-9165401  
Logic Symbol  
DS100294-1  
Pin Names  
Description  
E1, E2  
S0, S1  
MR  
Enable Inputs (Active LOW)  
Select Inputs  
Master Reset  
D
na–Dnd  
Data Inputs  
Qa–Qd  
Qa–Qd  
Data Outputs  
Complementary Data Outputs  
Connection Diagrams  
24-Pin DIP  
24-Pin Quad Cerpak  
DS100294-3  
DS100294-2  
© 1998 National Semiconductor Corporation  
DS100294  
www.national.com  

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