Datasheet > 存储 > EEPROM> NM25W040ENX

NM25W040ENX

更新时间： 2024-09-16 03:34:31

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
10页	105K
描述
4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)

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中文翻译

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NM25W040ENX 数据手册

March 1999

NM25C040

4K-Bit Serial CMOS EEPROM

(Serial Peripheral Interface (SPI) Synchronous Bus)

General Description

Features

The NM25C040 is a 4096-bit CMOS EEPROM with an SPI

compatible serial interface. The NM25C040 is designed for data

storage in applications requiring both non-volatile memory and in-

systemdataupdates. ThisEEPROMiswellsuitedforapplications

using the 68HC11 series of microcontrollers that support the SPI

interface for high speed communication with peripheral devices

via a serial bus to reduce pin count. The NM25C040 is imple-

mented in Fairchild Semiconductor’s floating gate CMOS process

that provides superior endurance and data retention.

■ 2.1 MHz clock rate @ 2.7V to 5.5V

■ 4096 bits organized as 512 x 8

■ Multiple chips on the same 3-wire bus with separate chip

select lines

■ Self-timed programming cycle

■ Simultaneous programming of 1 to 4 bytes at a time

■ Status register can be polled during programming to monitor

READY/BUSY

The serial data transmission of this device requires four signal

lines to control the device operation: Chip Select (CS), Clock

(SCK), Data In (SI), and Serial Data Out (SO). All programming

cycles are completely self-timed and do not require an erase

before WRITE.

■ Write Protect (WP) pin and write disable instruction for both

hardware and software write protection

■ Block write protect feature to protect against accidental

writes

■ Endurance: 1,000,000 data changes

BLOCK WRITE protection is provided by programming the STA-

TUS REGISTER with one of four levels of write protection.

Additionally, separate WRITE enable and WRITE disable instruc-

tions are provided for data protection.

■ Data retention greater than 40 years

■ Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP

Hardware data protection is provided by the WP pin to protect

against inadvertent programming. The HOLD pin allows the serial

communication to be suspended without resetting the serial

sequence.

Block Diagram

HOLD

SCK

V_CC

V_SS

Instruction

Decoder

Control Logic

and Clock

Instruction

Generators

Program

Enable

Address

Counter/

High Voltage

Generator

and

Program

Timer

V_PP

EEPROM Array

4096 Bits

(512 x 8)

Decoder

1 of 512

Read/Write Amps

Data In/Out Register

8 Bits

Data Out

Buffer

Non-Volatile

Status Register

DS012401-1

NM25C040 Rev. D.1

www.fairchildsemi.com

12 3 4 5 6 7...10

中文翻译

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NM25W040LEN	FAIRCHILD	获取价格	4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus)
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