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NM25C640LM8X PDF预览

NM25C640LM8X

更新时间： 2024-09-16 13:02:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 97K
描述
EEPROM, 8KX8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, SOIC-8

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NM25C640LM8X 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.78
其他特性：DATA RETENTION > 40 YEARS数据保留时间-最小值：40
JESD-30 代码：R-PDSO-G8长度：4.9 mm
内存密度：65536 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端子数量：8字数：8192 words
字数代码：8000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：8KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
认证状态：Not Qualified座面最大高度：1.75 mm
串行总线类型：SPI最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

NM25C640LM8X 数据手册

 浏览型号NM25C640LM8X的Datasheet PDF文件第2页浏览型号NM25C640LM8X的Datasheet PDF文件第3页浏览型号NM25C640LM8X的Datasheet PDF文件第4页浏览型号NM25C640LM8X的Datasheet PDF文件第5页浏览型号NM25C640LM8X的Datasheet PDF文件第6页浏览型号NM25C640LM8X的Datasheet PDF文件第7页 
PRELIMINARY  
March 1999  
NM25C640  
64K-Bit Serial CMOS EEPROM  
(Serial Peripheral Interface (SPI) Synchronous Bus)  
General Description  
Features  
The NM25C640 is a 65,536-bit CMOS EEPROM with an SPI  
compatible serial interface. The NM25C640 is designed for data  
storage in applications requiring both non-volatile memory and in-  
systemdataupdates. ThisEEPROMiswellsuitedforapplications  
using the 68HC11 series of microcontrollers that support the SPI  
interface for high speed communication with peripheral devices  
via a serial bus to reduce pin count. The NM25C640 is imple-  
mented in Fairchild Semiconductor’s floating gate CMOS process  
that provides superior endurance and data retention.  
■ 2.75 MHz clock rate @ 4.5V to 5.5V  
2.1 MHz @ 2.7V to 4.5V  
■ 65,536 bits organized as 8,192 x 8  
■ Multiple chips on the same 3-wire bus with separate chip  
select lines  
■ Self-timed programming cycle  
■ Simultaneous programming of 1 to 32 bytes at a time  
■ Status register can be polled during programming to monitor  
READY/BUSY  
The serial data transmission of this device requires four signal  
lines to control the device operation: Chip Select (CS), Clock  
(SCK), Data In (SI), and Serial Data Out (SO). All programming  
cycles are completely self-timed and do not require an erase  
before WRITE.  
■ Write Protect (WP) pin and write disable instruction for both  
hardware and software write protection  
■ Block write protect feature to protect against accidental  
writes  
BLOCK WRITE protection is provided by programming the STA-  
TUS REGISTER with one of four levels of write protection.  
Additionally, separate WRITE enable and WRITE disable instruc-  
tions are provided for data protection.  
■ Endurance: 1,000,000 data changes  
■ Data retention greater than 40 years  
■ Packages available: 8-pin DIP or 8-Pin SO  
Hardware data protection is provided by the WP pin to protect  
against inadvertent programming. The HOLD pin allows the serial  
communication to be suspended without resetting the serial  
sequence.  
Block Diagram  
CS  
HOLD  
SCK  
VCC  
VSS  
Instruction  
Decoder  
Control Logic  
and Clock  
WP  
Instruction  
SI  
Generators  
Register  
Program  
Enable  
Address  
Counter/  
Register  
High Voltage  
Generator  
and  
Program  
Timer  
VPP  
EEPROM Array  
65,536 Bits  
(8,192 x 8)  
Decoder  
1 of 8,192  
Read/Write Amps  
Data In/Out Register  
8 Bits  
Data Out  
Buffer  
SO  
Non-Volatile  
Status Register  
DS500041-1  
1
© 1999 Fairchild Semiconductor Corporation  
NM25C640 Rev. D.2  
www.fairchildsemi.com  
1234567...10

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