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NM25C160LN PDF预览

NM25C160LN

更新时间： 2024-11-03 23:54:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 104K
描述
SPI Serial EEPROM

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中文翻译

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NM25C160LN 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP8,.3针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.68
其他特性：DATA RETENTION > 40 YEARS数据保留时间-最小值：40
耐久性：1000000 Write/Erase CyclesJESD-30 代码：R-PDIP-T8
JESD-609代码：e0长度：9.817 mm
内存密度：16384 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端子数量：8字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：2KX8封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP8,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：SERIAL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
座面最大高度：5.08 mm串行总线类型：SPI
最大待机电流：0.00001 A子类别：EEPROMs
最大压摆率：0.003 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mm写保护：HARDWARE/SOFTWARE
Base Number Matches：1

NM25C160LN 数据手册

 浏览型号NM25C160LN的Datasheet PDF文件第2页浏览型号NM25C160LN的Datasheet PDF文件第3页浏览型号NM25C160LN的Datasheet PDF文件第4页浏览型号NM25C160LN的Datasheet PDF文件第5页浏览型号NM25C160LN的Datasheet PDF文件第6页浏览型号NM25C160LN的Datasheet PDF文件第7页 
March 1999  
NM25C160  
16K-Bit Serial CMOS EEPROM  
(Serial Peripheral Interface (SPI) Synchronous Bus)  
General Description  
Features  
The NM25C160 is a 16,384-bit CMOS EEPROM with an SPI  
compatible serial interface. The NM25C160 is designed for data  
storage in applications requiring both non-volatile memory and in-  
systemdataupdates. ThisEEPROMiswellsuitedforapplications  
using the 68HC11 series of microcontrollers that support the SPI  
interface for high speed communication with peripheral devices  
via a serial bus to reduce pin count. The NM25C160 is imple-  
mented in Fairchild Semiconductor’s floating gate CMOS process  
that provides superior endurance and data retention.  
■ 2.1 MHz clock rate @ 2.7V to 5.5V  
■ 16,384 bits organized as 2,048 x 8  
■ Multiple chips on the same 3-wire bus with separate chip  
select lines  
■ Self-timed programming cycle  
■ Simultaneous programming of 1 to 16 bytes at a time  
■ Status register can be polled during programming to monitor  
READY/BUSY  
The serial data transmission of this device requires four signal  
lines to control the device operation: Chip Select (CS), Clock  
(SCK), Data In (SI), and Serial Data Out (SO). All programming  
cycles are completely self-timed and do not require an erase  
before WRITE.  
■ Write Protect (WP) pin and write disable instruction for both  
hardware and software write protection  
■ Block write protect feature to protect against accidental  
writes  
■ Endurance: 1,000,000 data changes  
BLOCK WRITE protection is provided by programming the STA-  
TUS REGISTER with one of four levels of write protection.  
Additionally, separate WRITE enable and WRITE disable instruc-  
tions are provided for data protection.  
■ Data retention greater than 40 years  
■ Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP  
Hardware data protection is provided by the WP pin to protect  
against inadvertent programming. The HOLD pin allows the serial  
communication to be suspended without resetting the serial  
sequence.  
Block Diagram  
CS  
HOLD  
SCK  
VCC  
VSS  
Instruction  
Decoder  
Control Logic  
and Clock  
WP  
Instruction  
SI  
Generators  
Register  
Program  
Enable  
Address  
Counter/  
Register  
High Voltage  
Generator  
and  
Program  
Timer  
VPP  
EEPROM Array  
16,384 Bits  
(2048 x 8)  
Decoder  
1 of 2048  
Read/Write Amps  
Data In/Out Register  
8 Bits  
Data Out  
Buffer  
SO  
Non-Volatile  
Status Register  
DS012402-1  
1
© 1999 Fairchild Semiconductor Corporation  
NM25C160 Rev. D.1  
www.fairchildsemi.com  
1234567...10

中文翻译

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