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NM24W08TLEN PDF预览

NM24W08TLEN

更新时间: 2024-09-24 13:11:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 108K
描述
EEPROM, 2KX8, Serial, CMOS, PDIP8

NM24W08TLEN 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.84
Is Samacsys:N最大时钟频率 (fCLK):0.1 MHz
JESD-30 代码:R-PDIP-T8内存密度:16384 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:SERIAL认证状态:Not Qualified
串行总线类型:I2C最大供电电压 (Vsup):4.5 V
最小供电电压 (Vsup):2.7 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子位置:DUAL
最长写入周期时间 (tWC):15 msBase Number Matches:1

NM24W08TLEN 数据手册

 浏览型号NM24W08TLEN的Datasheet PDF文件第2页浏览型号NM24W08TLEN的Datasheet PDF文件第3页浏览型号NM24W08TLEN的Datasheet PDF文件第4页浏览型号NM24W08TLEN的Datasheet PDF文件第5页浏览型号NM24W08TLEN的Datasheet PDF文件第6页浏览型号NM24W08TLEN的Datasheet PDF文件第7页 
PRELIMINARY  
March 1999  
NM24Wxx  
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface  
Serial EEPROM with Full Array Write Protect  
General Description  
Features  
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-  
tively, of CMOS non-volatile electrically erasable memory. These  
devices conform to all specifications in the IIC 2-wire protocol and  
are designed to minimize device pin count, and simplify PC board  
layout requirements.  
Hardware Write Protect for entire memory  
Low Power CMOS  
200µA active current typical  
10µA standby current typical  
1µA standby typical (L)  
0.1µA standby typical (LZ)  
The entire ememory can be disabled (Write Protected) by con-  
nectingtheWPpintoVCC.Thememorythenbecomesunalterable  
IIC Compatible interface  
unless WP is switched to VSS  
.
— Provides bidirectional data transfer protocol  
Sixteen byte page write mode  
— Minimizes total write time per byte  
This communications protocol uses CLOCK (SCL) and DATA  
I/O (SDA) lines to synchronously clock data between the master  
(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).  
The Standard IIC protocol allows for a maximum of 16K of  
EEPROM memory which is supported by Fairchild's family in 2K,  
4K, 8K, and 16K devices, allowing the user to configure the  
memory as the application requires with any combination of  
EEPROMs.  
Self timed write cycle  
— Typical write cycle time of 6ms  
Endurance: 1,000,000 data changes  
Data retention greater than 40 years  
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP  
Available in three temperature ranges  
- Commercial: 0° to +70°C  
Fairchild EEPROMs are designed and tested for applications  
requiringhighendurance, highreliabilityandlowpowerconsump-  
tion.  
- Extended (E): -40° to +85C  
- Automotive (V): -40° to +125°C  
Block Diagram  
V
CC  
V
SS  
WP  
H.V. GENERATION  
TIMING &CONTROL  
START CYCLE  
START  
STOP  
SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER &  
COMPARATOR  
16/  
32/  
64/  
2
E
PROM  
ARRAY  
XDEC  
SCL  
128/  
LOAD  
INC  
A2  
A1  
A0  
WORD  
ADDRESS  
COUNTER  
0/1/2/3  
4
16  
4
R/W  
YDEC  
Device Address Bits  
8
CK  
D
OUT  
DATA REGISTER  
D
IN  
DS500074-1  
1
© 1999 Fairchild Semiconductor Corporation  
NM24Wxx Rev. C.2  
www.fairchildsemi.com  

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