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NM24C16DICE

更新时间： 2024-11-13 13:11:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 104K
描述
EEPROM, 2KX8, Serial, CMOS

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中文翻译

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NM24C16DICE 技术参数

生命周期：Obsolete包装说明：DIE,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.74
Is Samacsys：N最大时钟频率 (fCLK)：0.1 MHz
JESD-30 代码：X-XUUC-N4内存密度：16384 bit
内存集成电路类型：EEPROM内存宽度：8
功能数量：1端子数量：4
字数：2048 words字数代码：2000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：UNSPECIFIED封装形式：UNCASED CHIP
并行/串行：SERIAL认证状态：Not Qualified
串行总线类型：I2C最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：NO LEAD
端子位置：UPPER最长写入周期时间 (tWC)：10 ms
Base Number Matches：1

NM24C16DICE 数据手册

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February 2000  
NM24C16/17 – 16K-Bit Standard 2-Wire Bus  
Interface Serial EEPROM  
General Description  
Features  
The NM24C16/17 devices are 16,384 bits of CMOS non-volatile  
electrically erasable memory. These devices conform to all speci-  
fications in the Standard IIC 2-wire protocol and are designed to  
minimize device pin count, and simplify PC board layout require-  
ments.  
I Extended operating voltage 2.7V – 5.5V  
I 400 KHz clock frequency (F) at 2.7V - 5.5V  
I 200µA active current typical  
10µA standby current typical  
1µA standby current typical (L)  
0.1µA standby current typical (LZ)  
Theupperhalf(upper8Kbit)ofthememoryoftheNM24C17canbe  
write protected by connecting the WP pin to VCC. This section of  
I IIC compatible interface  
memory then becomes unalterable unless WP is switched to VSS  
.
– Provides bi-directional data transfer protocol  
This communications protocol uses CLOCK (SCL) and DATA  
I/O (SDA) lines to synchronously clock data between the master  
(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).  
The Standard IIC protocol allows for a maximum of 16K of  
EEPROM memory which is supported by the Fairchild family in  
2K, 4K, 8K, and 16K devices, allowing the user to configure the  
memory as the application requires with any combination of  
EEPROMs. In order to implement higher EEPROM memory  
densities on the IIC bus, the Extended IIC protocol must be used.  
(Refer to the NM24C32 or NM24C65 datasheets for more infor-  
mation.)  
I Schmitt trigger inputs  
I Sixteen byte page write mode  
– Minimizes total write time per byte  
I Self timed write cycle  
Typical write cycle time of 6ms  
I Hardware Write Protect for upper half (NM24C17 only)  
I Endurance: 1,000,000 data changes  
I Data retention greater than 40 years  
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP  
I Available in three temperature ranges  
- Commercial: 0° to +70°C  
Fairchild EEPROMs are designed and tested for applications requir-  
ing high endurance, high reliability and low power consumption.  
- Extended (E): -40° to +85C  
- Automotive (V): -40° to +125°C  
Block Diagram  
V
CC  
V
SS  
WP  
H.V. GENERATION  
TIMING &CONTROL  
START  
STOP  
SDA  
LOGIC  
CONTROL  
LOGIC  
SLAVE ADDRESS  
REGISTER  
2
E
PROM  
XDEC  
ARRAY  
SCL  
WORD  
ADDRESS  
COUNTER  
R/W  
YDEC  
CK  
D
OUT  
DATA REGISTER  
D
IN  
DS500072-1  
1
© 1998 Fairchild Semiconductor Corporation  
NM24C16/17 Rev. G  
www.fairchildsemi.com  
1234567...14

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