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NLV74VHCU04DTR2G PDF预览

NLV74VHCU04DTR2G

更新时间: 2024-11-29 11:01:47
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器栅极
页数 文件大小 规格书
6页 150K
描述
Unbuffered Hex Inverter

NLV74VHCU04DTR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSSOP, TSSOP14,.25
Reach Compliance Code:compliantFactory Lead Time:45 weeks
风险等级:5.65系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
湿度敏感等级:1功能数量:6
输入次数:1端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:2/5.5 VProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:AEC-Q100
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

NLV74VHCU04DTR2G 数据手册

 浏览型号NLV74VHCU04DTR2G的Datasheet PDF文件第2页浏览型号NLV74VHCU04DTR2G的Datasheet PDF文件第3页浏览型号NLV74VHCU04DTR2G的Datasheet PDF文件第4页浏览型号NLV74VHCU04DTR2G的Datasheet PDF文件第5页浏览型号NLV74VHCU04DTR2G的Datasheet PDF文件第6页 
MC74VHCU04  
Hex Inverter  
(Unbuffered)  
The MC74VHCU04 is an advanced high speed CMOS unbuffered  
inverter fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
The inputs tolerate voltages up to 7.0 V, allowing the interface of  
5.0 V systems to 3.0 V systems.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
14  
1
SOIC14  
D SUFFIX  
CASE 751A  
High Speed: t = 3.5 ns (Typ) at V = 5.0 V  
Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
High Noise Immunity: V  
PD  
CC  
VHCU04G  
AWLYWW  
CC  
A
1
= V  
= 10% V (Min.)  
NIH  
NIL  
CC  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
14  
Designed for 2.0 V to 5.5 V Operating Range  
VHCU  
04  
TSSOP14  
DT SUFFIX  
CASE 948G  
Low Noise: V  
= 0.8 V (Max)  
OLP  
ALYWG  
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
G
1
ESD Performance:  
Human Body Model > 2000 V;  
Machine Model > 200 V  
Chip Complexity: 12 FETs or 3 Equivalent Gates  
PbFree Packages are Available*  
14  
SOEIAJ14  
M SUFFIX  
CASE 965  
VHCU04  
ALYWG  
1
1
1
3
5
2
4
6
A1  
A2  
A3  
Y1  
Y2  
Y3  
A
= Assembly Location  
WL, L = Wafer Lot  
Y, YY = Year  
WW, W = Work Week  
G or G = PbFree Package  
(Note: Microdot may be in either location)  
Y = A  
FUNCTION TABLE  
9
8
10  
12  
A4  
A5  
A6  
Y4  
Y5  
Y6  
Inputs  
A
Outputs  
Y
11  
13  
L
H
L
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 1. Logic Diagram  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 Rev. 4  
MC74VHCU04/D  

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