Datasheet > NLV74VHCT32ADTR2G

NLV74VHCT32ADTR2G

更新时间： 2024-11-26 11:01:47

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
7页	133K
描述
Quad 2-Input OR Gate / CMOS Logic Level Shifter with LSTTL-Compatible Inputs

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MC74VHCT32A

Quad 2-Input OR Gate /

CMOS Logic Level Shifter

with LSTTL − Compatible Inputs

The MC74VHCT32A is an advanced high speed CMOS 2−input

OR gate fabricated with silicon gate CMOS technology. It achieves

high speed operation similar to equivalent Bipolar Schottky TTL

while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output.

The device input is compatible with TTL−type input thresholds and

the output has a full 5.0 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the

input, allowing the device to be used as a logic−level translator from

3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic

to 3.0 V CMOS Logic while operating at the high−voltage power

supply.

http://onsemi.com

MARKING

DIAGRAMS^†

SOIC−14

D SUFFIX

CASE 751A

VHCT32AG

AWLYWW

The MC74VHCT32A input structure provides protection when

voltages up to 7.0 V are applied, regardless of the supply voltage. This

allows the MC74VHCT32A to be used to interface 5.0 V circuits to

3.0 V circuits. The output structures also provide protection when

VHCT

32A

TSSOP−14

DT SUFFIX

CASE 948G

ALYW

ꢀ

= 0 V. These input and output structures help prevent device

destruction caused by supply voltage − input/output voltage mismatch,

battery backup, hot insertion, etc.

Features

SOEIAJ−14

M SUFFIX

CASE 965

74VHCT32

ALYWG

• High Speed: t = 3.8 ns (Typ) at V = 5.0 V

• Low Power Dissipation: I = 2 mA (Max) at T = 25°C

• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

WL, L

= Assembly Location

= Wafer Lot

• Designed for 2.0 V to 5.5 V Operating Range

= Year

WW, W = Work Week

G or = Pb−Free Package

• Low Noise: V

= 0.8 V (Max)

OLP

ꢀ

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300 mA

(Note: Microdot may be in either location)

• ESD Performance:

†For additional marking information, refer to

Application Note AND8002/D.

Human Body Model > 2000 V;

Machine Model > 200 V

• These Devices are Pb−Free and are RoHS Compliant

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Publication Order Number:

May, 2011 − Rev. 4

MC74VHCT32A/D

12 3 4 5 6 7

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