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NLV74VHCT00ADTR2G PDF预览

NLV74VHCT00ADTR2G

更新时间: 2024-11-29 11:01:47
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 95K
描述
Quad 2-Input NAND Gate

NLV74VHCT00ADTR2G 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:TSSOP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.74系列:HCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm逻辑集成电路类型:NAND GATE
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):17.5 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

NLV74VHCT00ADTR2G 数据手册

 浏览型号NLV74VHCT00ADTR2G的Datasheet PDF文件第2页浏览型号NLV74VHCT00ADTR2G的Datasheet PDF文件第3页浏览型号NLV74VHCT00ADTR2G的Datasheet PDF文件第4页浏览型号NLV74VHCT00ADTR2G的Datasheet PDF文件第5页浏览型号NLV74VHCT00ADTR2G的Datasheet PDF文件第6页浏览型号NLV74VHCT00ADTR2G的Datasheet PDF文件第7页 
MC74VHCT00A  
Quad 2-Input NAND Gate  
The MC74VHCT00A is an advanced high speed CMOS 2−input  
NAND gate fabricated with silicon gate CMOS technology. It  
achieves high speed operation while maintaining CMOS low power  
dissipation.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and the  
output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3.0 V  
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHCT00A input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHCT00A to be used to interface 5 V circuits to 3 V  
http://onsemi.com  
MARKING DIAGRAMS  
14  
14  
VHCT00AG  
AWLYWW  
1
SOIC−14  
D SUFFIX  
1
CASE 751A  
14  
circuits. The output structures also provide protection when V = 0 V.  
CC  
14  
VHCT  
00A  
These input and output structures help prevent device destruction caused  
by supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
1
ALYWG  
TSSOP−14  
DT SUFFIX  
CASE 948G  
G
1
High Speed: t = 5.0 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 2 μA (Max) at T = 25°C  
CC  
A
A
= Assembly Location  
= Year  
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
WL, L = Wafer Lot  
YY, Y  
WW, W = Work Week  
IL  
IH  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Designed for 3.0 V to 5.5 V Operating Range  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
Low Noise: V  
= 0.8 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: 48 FETs or 12 Equivalent Gates  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
dimensions section on page 6 of this data sheet.  
These Devices are Pb−Free and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
October, 2014 − Rev. 6  
MC74VHCT00A/D  

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