Datasheet > NLV74VHC126DR2G

NLV74VHC126DR2G

更新时间： 2024-11-29 11:01:43

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
9页	128K
描述
Quad Bus Buffer, 3-State

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NLV74VHC126DR2G 数据手册

MC74VHC126

Quad Bus Buffer

with 3−State Control Inputs

The MC74VHC126 is a high speed CMOS quad bus buffer

fabricated with silicon gate CMOS technology. It achieves

noninverting high speed operation similar to equivalent Bipolar

Schottky TTL while maintaining CMOS low power dissipation.

The MC74VHC126 requires the 3−state control input (OE) to be set

Low to place the output into high impedance.

http://onsemi.com

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

14−LEAD SOIC

D SUFFIX

CASE 751A

14−LEAD TSSOP

DT SUFFIX

CASE 948G

• High Speed: t = 3.8 ns (Typ) at V = 5.0 V

• Low Power Dissipation: I = 4.0 μA (Max) at T = 25°C

• High Noise Immunity: V

= V

= 28% V

PIN CONNECTIONS

NIH

NIL CC

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

OE1

13 OE4

• Designed for 2.0 V to 5.5 V Operating Range

• Low Noise: V

= 0.8 V (Max)

OLP

OE2

11 Y4

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300 mA

10 OE3

• ESD Performance: HBM > 2000 V; Machine Model > 200 V

• Chip Complexity: 72 FETs or 18 Equivalent Gates

• These Devices are Pb−Free and are RoHS Compliant

GND

(Top View)

ORDERING INFORMATION

Device

MC74VHC126DR2G

Package

Shipping

2500 Units/Reel

SOIC

MC74VHC126DTR2G TSSOP 2500 Units/Reel

DEVICE MARKING INFORMATION

See general marking information in the device marking

section on page 7 of this data sheet.

Publication Order Number:

May, 2011 − Rev. 5

MC74VHC126/D

12 3 4 5 6 7...9

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