5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> NLV74LCX573DTR2G
NLV74LCX573DTR2G PDF预览

NLV74LCX573DTR2G

更新时间： 2024-11-26 11:01:47
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路总线驱动器总线收发器
页数 文件大小 规格书
8页 94K
描述
Low Voltage CMOS Octal Transparent Latch Flow Through Pinout

阅读下载

中文翻译

获取价格

NLV74LCX573DTR2G 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：4 weeks
风险等级：5.61系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：8 ns
传播延迟（tpd）：10.5 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

NLV74LCX573DTR2G 数据手册

 浏览型号NLV74LCX573DTR2G的Datasheet PDF文件第2页浏览型号NLV74LCX573DTR2G的Datasheet PDF文件第3页浏览型号NLV74LCX573DTR2G的Datasheet PDF文件第4页浏览型号NLV74LCX573DTR2G的Datasheet PDF文件第5页浏览型号NLV74LCX573DTR2G的Datasheet PDF文件第6页浏览型号NLV74LCX573DTR2G的Datasheet PDF文件第7页 
MC74LCX573  
Low−Voltage CMOS  
Octal Transparent Latch  
Flow Through Pinout  
With 5 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
http://onsemi.com  
MARKING  
The MC74LCX573 is a high performance, non−inverting octal  
transparent latch operating from a 2.3 to 3.6 V supply. High  
impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
DIAGRAMS  
20  
SOIC−20  
DW SUFFIX  
CASE 751D  
switching noise performance. A V specification of 5.5 V allows  
I
LCX573  
AWLYYWWG  
20  
MC74LCX573 inputs to be safely driven from 5.0 V devices.  
The MC74LCX573 contains 8 D−type latches with 3−state standard  
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn  
inputs enters the latches. In this condition, the latches are transparent,  
i.e., a latch output will change state each time its D input changes.  
When LE is LOW, the latches store the information that was present  
on the D inputs a setup time preceding the HIGH−to−LOW transition  
of LE. The 3−state standard outputs are controlled by the Output  
Enable (OE) input. When OE is LOW, the standard outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches. The LCX573 flow through design facilitates easy PC  
board layout.  
1
1
20  
LCX  
573  
TSSOP−20  
DT SUFFIX  
20  
ALYWG  
CASE 948E  
1
G
1
20  
SOEIAJ−20  
M SUFFIX  
CASE 967  
1
Features  
74LCX573  
AWLYWWG  
• Designed for 2.3 to 3.6 V V Operation  
• 5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic  
CC  
20  
1
• Supports Live Insertion and Withdrawal  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
• I  
Specification Guarantees High Impedance When V = 0 V  
CC  
OFF  
• LVTTL Compatible  
W, WW = Work Week  
• LVCMOS Compatible  
• 24 mA Balanced Output Sink and Source Capability  
G
G
= Pb−Free Package  
= Pb−Free Package  
(Note: Microdot may be in either location)  
• Near Zero Static Supply Current in All Three Logic States (10 mA)  
Substantially Reduces System Power Requirements  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
• Latchup Performance Exceeds 500 mA  
• ESD Performance:  
Human Body Model >2000 V  
Machine Model >200 V  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
May, 2005 − Rev. 7  
MC74LCX573/D  
12345678

中文翻译

下载PDF

与NLV74LCX573DTR2G相关器件

型号 品牌 获取价格 描述 数据表
NLV74LCX574DTR2G ONSEMI

获取价格

 		Low Voltage CMOS Octal D Flip-Flop Flow Through Pinout
NLV74LVX08DTR2G ONSEMI

获取价格

 		Quad 2-Input AND Gate
NLV74LVX14DTR2G ONSEMI

获取价格

 		Hex Inverter with Schmitt Trigger Input
NLV74LVX573DTR2G ONSEMI

获取价格

 		Octal D Latch 3-State Outputs
NLV74LVX8051DR2G ONSEMI

获取价格

 		Analog Multiplexer/Demultiplexer (Mux/Demux)
NLV74LVX8051DTR2G ONSEMI

获取价格

 		Analog Multiplexer/Demultiplexer (Mux/Demux)
NLV74VHC00DTR2G ONSEMI

获取价格

 		Quad 2-Input NAND Gate
NLV74VHC02DTR2G ONSEMI

获取价格

 		Quad 2-Input NOR Gate
NLV74VHC04DTR2G ONSEMI

获取价格

 		六路逆变器
NLV74VHC08DTRG ONSEMI

获取价格

 		四路 2 输入 AND 门极

与NLV74LCX573DTR2G相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证