Datasheet > NLV14001UBDG

NLV14001UBDG

更新时间： 2024-09-16 01:09:07

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
6页	144K
描述
UB-Suffix Series CMOS Gates

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NLV14001UBDG 数据手册

MC14001UB, MC14011UB

UB-Suffix Series

CMOS Gates

The UB Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired. The UB set of

CMOS gates are inverting non−buffered functions.

http://onsemi.com

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Linear and Oscillator Applications

SOIC−14

D SUFFIX

CASE 751A

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs

MARKING DIAGRAM

• Pin−for−Pin Replacements for Corresponding CD4000 Series UB

Suffix Devices

140xxUG

AWLYWW

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

• This Device is Pb−Free and is RoHS Compliant

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

= Year

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

−0.5 to +18.0

Unit

WW, W = Work Week

= Pb−Free Package

DC Supply Voltage Range

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

I , I

in out

Input or Output Current

(DC or Transient) per Pin

Power Dissipation, per Package

(Note 1)

500

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

stg

Lead Temperature

(8−Second Soldering)

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be affected.

1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V ≤ (V or V ) ≤ V .

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Publication Order Number:

July, 2014 − Rev. 10

MC14001UB/D

12 3 4 5 6

中文翻译

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