NLSX3018
8-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3018 is a 8−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O V − and I/O
http://onsemi.com
CC
V −ports are designed to track two different power supply rails, V
L
CC
MARKING
DIAGRAMS
and V respectively. The V supply rail is configurable from 1.3 V
L
CC
to 4.5 V while the V supply rail is configurable from 0.9 V to (V
L
CC
− 0.4) V. This allows lower voltage logic signals on the V side to be
L
UQFN20
MU SUFFIX
CASE 517AK
LAM
G
translated into higher voltage logic signals on the V
side, and
CC
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
LA = Specific Device Code
M
= Date Code
G
= Pb−Free Package
currents from both V and V . The EN signal is designed to track
CC
L
V .
L
20
SOIC−20
DW SUFFIX
CASE 751D
Features
NLSX3018
AWLYYWWG
• Wide High−Side V Operating Range: 1.3 V to 4.5 V
CC
Wide Low−Side V Operating Range: 0.9 V to (V − 0.4) V
L
CC
1
• High−Speed with 100 Mb/s Guaranteed Date Rate for V > 1.6 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Powerup Sequencing
• Small packaging: 4.0 mm x 2.0 mm UQFN20
• This is a Pb−Free Device
L
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
NLSX
TSSOP−20
DT SUFFIX
CASE 948E
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
3018
ALYWG
G
PIN ASSIGNMENT
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
I/O V 1
I/O V
I/O V
I/O V
1
1
2
20
19
18
L
CC
I/O V 2
2
CC
3
CC
4
CC
L
3
I/O V 3
L
(Note: Microdot may be in either location)
I/O V 4
4
17 I/O V
L
V
V
CC
5
16
15
L
EN
6
GND
I/O V
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
I/O V 5
5
CC
6
CC
7
CC
8
CC
7
14
L
I/O V 6
8
13 I/O V
L
9
12
11
I/O V 7
I/O V
I/O V
L
10
I/O V 8
L
(Top View)
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
June, 2009 − Rev. 0
NLSX3018/D