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NL37WZ07US PDF预览

NL37WZ07US

更新时间: 2024-09-25 03:46:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 84K
描述
Triple Buffer with Open Drain Outputs

NL37WZ07US 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:VSSOP, TSSOP8,.12,20
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.22系列:37WZ
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:2.3 mm负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.024 A
湿度敏感等级:1功能数量:3
输入次数:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:VSSOP封装等效代码:TSSOP8,.12,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:3.3 VProp。Delay @ Nom-Sup:4.8 ns
传播延迟(tpd):7.8 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.9 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:2 mmBase Number Matches:1

NL37WZ07US 数据手册

 浏览型号NL37WZ07US的Datasheet PDF文件第2页浏览型号NL37WZ07US的Datasheet PDF文件第3页浏览型号NL37WZ07US的Datasheet PDF文件第4页浏览型号NL37WZ07US的Datasheet PDF文件第5页浏览型号NL37WZ07US的Datasheet PDF文件第6页浏览型号NL37WZ07US的Datasheet PDF文件第7页 
NL37WZ07  
Triple Buffer with Open  
Drain Outputs  
The NL37WZ07 is a high performance triple buffer with open drain  
outputs operating from a 1.65 V to 5.5 V supply.  
The internal circuit is composed of multiple stages, including an  
open drain output which provides the capability to set output  
switching level. This allows the NL37WZ07 to be used to interface 5  
http://onsemi.com  
V circuits to circuits of any voltage between V and 7 V using an  
external resistor and power supply.  
CC  
MARKING  
DIAGRAM  
Extremely High Speed: t 2.5 ns (typical) at V = 5 V  
PD  
CC  
8
Designed for 1.65 V to 5.5 V V Operation  
CC  
8
Over Voltage Tolerant Inputs  
D
1
L7  
LVTTL Compatible − Interface Capability with 5 V TTL Logic with  
= 3 V  
US8  
V
CC  
US SUFFIX  
CASE 493  
LVCMOS Compatible  
24 mA Output Sink Capability @ 3.0 V  
1
Near Zero Static Supply Current Substantially Reduces System  
L7 = Device Code  
D = Date Code  
Power Requirements  
Chip Complexity: FET = 72  
PIN ASSIGNMENT  
1
2
IN A1  
IN A1  
OUT Y3  
IN A2  
1
2
3
4
8
7
6
5
V
CC  
OUT Y3  
IN A2  
3
4
5
GND  
OUT Y1  
IN A3  
OUT Y2  
IN A3  
6
7
8
OUT Y1  
V
CC  
GND  
OUT Y2  
FUNCTION TABLE  
Figure 1. Pinout  
A Input  
Y Output  
L
L
Z
H
IN A1  
IN A2  
1
1
OUT Y1  
OUT Y2  
ORDERING INFORMATION  
1
IN A3  
OUT Y3  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
August, 2003 − Rev. 2  
NL37WZ07/D  

NL37WZ07US 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC3G07DCUTG4 TI

类似代替

TRIPLE BUFFER / DRIVER WITH OPEN DRAIN OUTPUTS
SN74LVC3G07DCUTE4 TI

类似代替

TRIPLE BUFFER / DRIVER WITH OPEN DRAIN OUTPUTS
SN74LVC3G07DCURE4 TI

类似代替

TRIPLE BUFFER / DRIVER WITH OPEN DRAIN OUTPUTS

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