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NL27WZ17MU1TCG PDF预览

NL27WZ17MU1TCG

更新时间: 2023-06-19 14:34:11
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器栅极
页数 文件大小 规格书
6页 54K
描述
双非反相缓冲器,带施密特触发器输入

NL27WZ17MU1TCG 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:UDFN-6Reach Compliance Code:compliant
风险等级:5.71系列:27WZ
JESD-30 代码:R-PDSO-N6长度:1.45 mm
负载电容(CL):50 pF逻辑集成电路类型:BUFFER
最大I(ol):0.024 A功能数量:2
输入次数:1端子数量:6
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:SOLCC6,.04,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TR
Prop。Delay @ Nom-Sup:7.5 ns传播延迟(tpd):15.6 ns
施密特触发器:YES座面最大高度:0.55 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):2.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL宽度:1 mm
Base Number Matches:1

NL27WZ17MU1TCG 数据手册

 浏览型号NL27WZ17MU1TCG的Datasheet PDF文件第2页浏览型号NL27WZ17MU1TCG的Datasheet PDF文件第3页浏览型号NL27WZ17MU1TCG的Datasheet PDF文件第4页浏览型号NL27WZ17MU1TCG的Datasheet PDF文件第5页浏览型号NL27WZ17MU1TCG的Datasheet PDF文件第6页 
NL27WZ17  
Dual Non−Inverting Schmitt  
Trigger Buffer  
The NL27WZ17 is a high performance dual buffer operating from a  
1.65 to 5.5 V supply. At V = 3.0 V, high impedance TTL compatible  
CC  
inputs significantly reduce current loading to input drivers while the TTL  
compatible outputs offer improved switching noise performance.  
http://onsemi.com  
Features  
Extremely High Speed: t 2.0 ns (typical) at V = 5.0 V  
PD  
CC  
Designed for 1.65 V to 5.5 V V Operation  
Overvoltage Tolerant Inputs  
SC−88/SOT−363/SC−70  
DF SUFFIX  
CC  
CASE 419B  
LVTTL Compatible − Interface Capability with 5.0 V TTL Logic  
with V = 3.0 V (2.7−3.3)  
CC  
LVCMOS Compatible  
MARKING DIAGRAM  
24 mA Balanced Output Sink and Source Capability at V = 3.0 V  
CC  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
MXd  
Chip Complexity: FET = 72; Equivalent Gate = 18  
Pb−Free Package is Available  
Pin 1  
d = Date Code  
6
5
4
OUT Y1  
1
2
IN A1  
GND  
V
CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
3
OUT Y2  
IN A2  
Figure 1. Pinout (Top View)  
1
1
IN A1  
OUT Y1  
OUT Y2  
IN A2  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
FUNCTION TABLE  
1
2
3
4
IN A1  
GND  
A Input  
Y Output  
L
L
IN A2  
OUT Y2  
H
H
5
6
V
CC  
OUT Y1  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
March, 2004 − Rev. 4  
NL27WZ17/D  

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