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NL27WZ14MU3TCG

更新时间： 2023-06-19 14:34:25
品牌 Logo 应用领域
安森美 - ONSEMI 栅逻辑集成电路栅极
页数 文件大小 规格书
6页 82K
描述
Dual Inverter with Schmitt Trigger Input

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中文翻译

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NL27WZ14MU3TCG 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：,Reach Compliance Code：compliant
风险等级：5.67逻辑集成电路类型：INVERTER
峰值回流温度（摄氏度）：NOT SPECIFIED处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

NL27WZ14MU3TCG 数据手册

 浏览型号NL27WZ14MU3TCG的Datasheet PDF文件第2页浏览型号NL27WZ14MU3TCG的Datasheet PDF文件第3页浏览型号NL27WZ14MU3TCG的Datasheet PDF文件第4页浏览型号NL27WZ14MU3TCG的Datasheet PDF文件第5页浏览型号NL27WZ14MU3TCG的Datasheet PDF文件第6页 
NL27WZ14  
Dual Schmitt−Trigger  
Inverter  
The NL27WZ14 is a high performance dual inverter with  
Schmitt−Trigger inputs operating from a 1.65 to 5.5 V supply.  
Pin configuration and function are the same as the NL27WZ04, but  
the inputs have hysteresis and, with its Schmitt trigger function, the  
NL27WZ14 can be used as a line receiver which will receive slow  
input signals. The NL27WZ14 is capable of transforming slowly  
changing input signals into sharply defined, jitter−free output signals.  
In addition, it has a greater noise margin than conventional inverters.  
The NL27WZ14 has hysteresis between the positive−going and the  
negative−going input thresholds (typically 1 V) which is determined  
internally by transistor ratios and is essentially insensitive to  
temperature and supply voltage variations.  
http://onsemi.com  
MARKING  
DIAGRAMS  
6
6
1
MA M G  
1
G
SC−88/SOT−363/SC70−6  
DF SUFFIX  
CASE 419B  
Features  
• Designed for 1.65 V to 5.5 V V Operation  
CC  
6
6
• Over Voltage Tolerant Inputs and Outputs  
MA M G  
• LVTTL Compatible − Interface Capability with 5 V TTL Logic  
1
G
with V = 3 V  
CC  
TSOP−6/SOT−23−6/SC59−6  
DT SUFFIX  
1
• LVCMOS Compatible  
• 24 mA Balanced Output Sink and Source Capability  
• Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
CASE 318G  
MA = Device Marking  
M
= Date Code*  
• Current Drive Capability is 24 mA at the Outputs  
• Chip Complexity: FET = 72  
• Pb−Free Packages are Available  
G
= Pb−Free Package  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
PIN ASSIGNMENT  
Pin  
Function  
6
5
4
OUT Y1  
1
2
IN A1  
GND  
1
IN A1  
2
3
GND  
IN A2  
V
CC  
4
5
6
OUT Y2  
V
CC  
3
IN A2  
OUT Y2  
OUT Y1  
Figure 1. Pinout (Top View)  
FUNCTION TABLE  
A Input  
Y Output  
L
H
L
H
IN A1  
IN A2  
1
OUT Y1  
OUT Y2  
1
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 9  
NL27WZ14/D  
123456

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