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NL27WZ14DTT3 PDF预览

NL27WZ14DTT3

更新时间: 2024-09-28 15:46:35
品牌 Logo 应用领域
安森美 - ONSEMI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
6页 123K
描述
DUAL 1-INPUT INVERT GATE, PDSO6, SC-59, SOT-23, TSOP-6

NL27WZ14DTT3 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP, TSOP6,.11,37针数:6
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.6JESD-30 代码:R-PDSO-G6
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:INVERTER最大I(ol):0.024 A
功能数量:2输入次数:1
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V传播延迟(tpd):8.1 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.5 mm
Base Number Matches:1

NL27WZ14DTT3 数据手册

 浏览型号NL27WZ14DTT3的Datasheet PDF文件第2页浏览型号NL27WZ14DTT3的Datasheet PDF文件第3页浏览型号NL27WZ14DTT3的Datasheet PDF文件第4页浏览型号NL27WZ14DTT3的Datasheet PDF文件第5页浏览型号NL27WZ14DTT3的Datasheet PDF文件第6页 
NL27WZ14  
Dual Schmitt-Trigger  
Inverter  
The NL27WZ14 is a high performance dual inverter with  
SchmittTrigger inputs operating from a 1.65 to 5.5 V supply.  
Pin configuration and function are the same as the NL27WZ04, but  
the inputs have hysteresis and, with its Schmitt trigger function, the  
NL27WZ14 can be used as a line receiver which will receive slow  
input signals. The NL27WZ14 is capable of transforming slowly  
changing input signals into sharply defined, jitterfree output signals.  
In addition, it has a greater noise margin than conventional inverters.  
The NL27WZ14 has hysteresis between the positivegoing and the  
negativegoing input thresholds (typically 1 V) which is determined  
internally by transistor ratios and is essentially insensitive to  
temperature and supply voltage variations.  
http://onsemi.com  
MARKING  
DIAGRAMS  
6
6
1
1
MA M G  
G
SC88/SOT363/SC706  
DF SUFFIX  
CASE 419B  
Features  
Designed for 1.65 V to 5.5 V V Operation  
CC  
6
6
Over Voltage Tolerant Inputs and Outputs  
MA M G  
LVTTL Compatible Interface Capability with 5 V TTL Logic  
1
G
with V = 3 V  
TSOP6  
DT SUFFIX  
CASE 318G  
CC  
1
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current Substantially Reduces System  
MA = Device Marking  
Power Requirements  
M
= Date Code*  
G
= PbFree Package  
Current Drive Capability is 24 mA at the Outputs  
Chip Complexity: FET = 72  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
PIN ASSIGNMENT  
These Devices are PbFree and are RoHS Compliant  
Pin  
Function  
1
2
3
4
5
6
IN A1  
GND  
IN A1  
GND  
IN A2  
1
2
3
6
5
4
OUT Y1  
IN A2  
OUT Y2  
V
CC  
V
CC  
OUT Y1  
OUT Y2  
FUNCTION TABLE  
A Input  
Y Output  
Figure 1. Pinout (Top View)  
L
H
L
H
IN A1  
IN A2  
1
1
OUT Y1  
OUT Y2  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
March, 2013 Rev. 13  
NL27WZ14/D  

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