NL17SZ74
Single D Flip Flop
The NL17SZ74 is a high performance, full function Edge triggered
D Flip Flop, with all the features of a standard logic device such as the
74LCX74.
Features
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• Extremely High Speed: t 2.6 ns (typical) at V = 5.0 V
• Designed for 1.65 V to 5.5 V V Operation
PD
CC
MARKING
DIAGRAM
CC
• 5.0 V Tolerant Inputs − Interface Capability with 5.0 V TTL Logic
• LVTTL Compatible
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
US8
US SUFFIX
CASE 493
MH M
G
• Near Zero Static Supply Current (10 mA) Substantially Reduces
System Power Requirements
• Replacement for NC7SZ74
• Tiny Ultra Small Package Only 2.1 X 3.0 mm
M
G
= Date Code
= Pb−Free Package
• High ESD Ratings: 2000 V Human Body Model
High ESD Ratings: 200 V Machine Model
• Chip Complexity: FET = 64
PINOUT DIAGRAM
• Pb−Free Packages are Available
1
8
7
6
5
CP
D
Q
V
CC
2
3
4
PR
CLR
Q
GND
TRUTH TABLE
Inputs
Outputs
PR CLR CP
D
Q
Q
Operating Mode
LOGIC DIAGRAM
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
Asynchronous Set
Asynchronous Clear
Undetermined
PR
H
H
H
H
↑
↑
h
l
H
L
L
H
7
Load and Read Register
Hold
D
2
Q
Q
5
3
H
H
↑
X
NC
NC
H
= High Voltage Level
1
CP
h
= High Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
6
L
l
= Low Voltage Level
V
CC
= 8, GND = 4
= Low Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
CLR
NC
X
= No Change
= High or Low Voltage Level and Transitions are Acceptable
= Low−to−High Transition
↑
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
↑
= Not a Low−to−High Transition
For I reasons, DO NOT FLOAT Inputs
CC
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 4
NL17SZ74/D