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NJW1104FC2-80 PDF预览

NJW1104FC2-80

更新时间: 2024-11-19 22:11:19
品牌 Logo 应用领域
NJRC 解码器商用集成电路信息通信管理
页数 文件大小 规格书
6页 88K
描述
DOLBY PRO LOGIC SURROUND DECODER

NJW1104FC2-80 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:80
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.81Is Samacsys:N
其他特性:IT ALSO REQUIRES 9V TO 13V ANALOG SUPPLY商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PQFP-G80长度:20 mm
功能数量:1端子数量:80
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
认证状态:Not Qualified座面最大高度:3 mm
最大压摆率:60 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

NJW1104FC2-80 数据手册

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NJW1104  
PPRELIMINARY  
DOLBY PRO LOGIC SURROUND DECODER  
n GENERAL DESCRIPTION  
n PACKAGE OUTLINE  
The NJW1104 is a surround processor including all of  
the necessary circuits of Dolby Pro Logic Surround  
decoder and digital delay.  
In addition to Dolby Pro Logic Surround function, it  
performs easily other surround function such as Hall, Live,  
Disco and others.  
NJW1104FC2-80  
NJW1104FC2  
Dolby and double-D symbol are trademarks of Dolby Laboratories Licensing Corporation.  
San Francisco, CA94103-4813.USA.  
This device is available only to licensees of Dolby Lab.  
Licensing and application information may be obtained from Dolby Lab.  
n FEATURES  
l Operating Voltage : VCC=10V(Analog Block), VDD=5V(Digital Block)  
l Digital Delay on chip  
l Serial Data Interface(3-wire)  
l Bi-CMOS Technology  
l Package Outline  
DATA, REQ, SCK  
QFP80, QFP100  
n FUNCTION  
[Dolby Pro Logic Surround]  
l Automatic input balance  
l Noise sequencer  
[Other Surround]  
l Surround Signal Selector  
(L+R, L-R, EXTIN)  
l Adaptive matrix  
l Center channel control  
l Front mixing control  
l Digital time delay  
(Wide band, Normal, Phantom, Off)  
l Modified B-type noise reduction  
l 7kHz low-pass filter  
(15,20,25,30,40,50,60msec.)  
[Other Function]  
l Digital auxiliary outputs  
l Dolby 3 stereo mode  
(AUX1-AUX10)  
l Digital time delay(15,20,25,30msec.)  
n SYSTEM BLOCK DIAGRAM  
LIN  
Center Mode  
LOUT  
Input Autobalance  
Noise Sequencer  
Adaptive Matrix  
RIN  
COUT  
ROUT  
L+R  
L-R  
Modified  
B-NR  
Delay  
EXTIN  
SOUT  
7KHz  
LPF  
MCU Interface  
ADD/SUB  
SW. Controller  
.
Ver.1.0  
- 1 -  

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