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NE76100_99

更新时间: 2024-11-20 03:46:43
品牌 Logo 应用领域
日电电子 - NEC /
页数 文件大小 规格书
8页 54K
描述
GENERAL PURPOSE GaAs MESFET

NE76100_99 数据手册

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GENERAL PURPOSE  
GaAs MESFET  
NE76100  
NOISE FIGURE & ASSOCIATED  
FEATURES  
GAIN vs. FREQUENCY  
VDS = 3 V, IDS = 10 mA  
LOW NOISE FIGURE:  
NF = 0.8 dB typical at f = 4 GHz  
24  
21  
18  
15  
12  
4
3.5  
HIGH ASSOCIATED GAIN:  
GA = 12.0 dB typical at f = 4 GHz  
3
Ga  
LG = 1.0 µm, WG = 400 µm  
2.5  
2
DESCRIPTION  
9
6
1.5  
1
NE76100 is a high performance gallium arsenide metal semi-  
conductorfieldeffecttransistorchip.Itslownoisefiguremakes  
this device appropriate for use in the second or third stages of  
low noise amplifiers operating in the 1-12 GHz frequency  
range. The device is fabricated using ion implantation for  
improved RF and DC performance, reliability, and uniformity.  
The NE76100 is suitable for a wide variety of commercial and  
industrial applications.  
NF  
0.5  
0
3
0
1
10  
20  
Frequency, f (GHz)  
NEC's stringent quality assurance and test procedures assure  
the highest reliability and performance.  
ELECTRICAL CHARACTERISTICS (TA = 25°C)  
PART NUMBER  
PACKAGE OUTLINE  
NE76100  
00 (CHIP)  
SYMBOLS  
NFOPT1  
GA1  
PARAMETERS AND CONDITIONS  
Noise Figure at VDS = 3 V, ID = 10 mA, f = 4 GHz  
Associated Gain at VDS = 3 V, ID = 10 mA, f = 4 GHz  
UNITS  
dB  
MIN  
TYP  
0.8  
MAX  
1.4  
dB  
12.0  
P1dB  
Output Power at 1 dB Gain Compression Point, f = 4 GHz  
VDS = 3 V, IDS = 10 mA  
dBm  
dBm  
12.5  
15.0  
VDS = 3 V, IDS = 30 mA  
G1dB  
Gain at P1dB, f = 4 GHz  
VDS = 3 V, IDS = 10 mA  
VDS = 3 V, IDS = 30 mA  
dB  
dB  
11.5  
13.5  
IDSS  
VP  
Saturated Drain Current at VDS = 3 V, VGS = 0  
Pinch Off Voltage at VDS = 3 V, ID = 100 mA  
Transconductance at VDS = 3 V, ID = 10 mA  
Gate to Source Leak Current at VGS = -5 V  
mA  
V
30  
-3.0  
20  
60  
-1.1  
45  
100  
-0.5  
gm  
mS  
µA  
IGSO  
1.0  
10  
2
RTH  
Thermal Resistance  
°C/W  
190  
Notes:  
1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects  
for 10 samples.  
2. Chip mounted on an infinite heat sink.  
California Eastern Laboratories  

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