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NE5520279A-T1-A PDF预览

NE5520279A-T1-A

更新时间: 2024-11-09 04:37:47
品牌 Logo 应用领域
CEL 晶体晶体管ISM频段放大器
页数 文件大小 规格书
8页 352K
描述
3.2 V, 2 W, L&S BAND MEDIUM POWER SILICON LD-MOSFET

NE5520279A-T1-A 数据手册

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NEC'S 3.2 V, 2 W, L&S BAND  
MEDIUM POWER SILICON LD-MOSFET  
NE5520279A  
FEATURES  
OUTLINE DIMENSIONS (Units in mm)  
• LOW COST PLASTIC SURFACE MOUNT PACKAGE:  
5.7x5.7x1.1 mm MAX  
PACKAGE OUTLINE 79A  
(Bottom View)  
4.2 MAX.  
Source  
1.5±0.2  
• HIGH OUTPUT POWER:  
Source  
+32 dBm TYP  
• HIGH LINEAR GAIN:  
Gate  
Drain  
Gate  
Drain  
10 dB TYP @ 1.8 GHz  
• HIGH POWER ADDED EFFICIENCY:  
45% TYP at 1.8 GHz  
• SINGLE SUPPLY:  
2.8 to 6.0 V  
0.4±0.15  
5.7 MAX.  
0.8 MAX.  
3.6±0.2  
DESCRIPTION  
APPLICATIONS  
NEC's NE5520279A is an N-Channel silicon power laterally  
diffused MOSFET specially designed as the power amplifier  
for mobile and fixed wireless applications. Die are manu-  
factured using NEC's NEWMOS technology (NEC's 0.6 μm  
WSi gate lateral MOSFET) and housed in a surface mount  
package.  
• DIGITAL CELLULAR PHONES:  
3.2 V DCS1800 Handsets  
• 0.7-2.5 GHz FIXED WIRELESS ACCESS  
• W-LAN  
• SHORT RANGE WIRELESS  
• RETAIL BUSINESS RADIO  
• SPECIAL MOBILE RADIO  
ELECTRICAL CHARACTERISTICS (TA = 25°C)  
PART NUMBER  
NE5520279A  
79A  
PACKAGE OUTLINE  
SYMBOLS  
POUT  
GL  
CHARACTERISTICS  
Output Power  
UNITS  
dBm  
dB  
MIN  
TYP  
32.0  
10  
MAX  
TEST CONDITIONS  
30.5  
f = 1.8 GHz, VDS = 3.2 V,  
IDSQ = 700 mA, PIN = 25 dBm, except  
PIN = 5 dBm for Linear Gain  
Linear Gain  
ηADD  
ID  
Power Added Efficiency  
Drain Current  
%
40  
45  
mA  
nA  
800  
IGSS  
Gate-to-Source Leakage Current  
100  
100  
VGS = 5.0 V  
VDS = 6.0 V  
IDSS  
Saturated Drain Current  
nA  
(Zero Gate Voltage Drain Current)  
VTH  
gm  
Gate Threshold Voltage  
Transconductance  
V
S
1.0  
15  
1.4  
1.3  
18  
1.9  
VDS = 3.5 V, IDS = 1 mA  
VDS = 3.5 V, IDS = 700 mA  
IDSS = 10 μA  
BVDSS  
RTH  
Drain-to-Source Breakdown Voltage  
Thermal Resistance  
V
°C/W  
8
Channel-to-Case  
Notes:  
1. DC performance is 100% testing. RF performance is testing several samples per wafer.  
Wafer rejection criteria for standard devices is 1 reject for several samples.  
2. Pin = 5 dBm  
California Eastern Laboratories  

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