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NDS331

更新时间: 2024-11-24 22:29:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管场效应晶体管
页数 文件大小 规格书
6页 62K
描述
N-Channel Logic Level Enhancement Mode Field Effect Transistor

NDS331 数据手册

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July 1996  
NDS331N  
N-Channel Logic Level Enhancement Mode Field Effect Transistor  
General Description  
Features  
These N-Channel logic level enhancement mode power field  
effect transistors are produced using Fairchild's proprietary,  
high cell density, DMOS technology. This very high density  
process is especially tailored to minimize on-state resistance.  
These devices are particularly suited for low voltage  
applications in notebook computers, portable phones, PCMCIA  
1.3 A, 20 V. RDS(ON) = 0.21 W @ VGS= 2.7 V  
RDS(ON) = 0.16 W @ VGS= 4.5 V.  
Industry standard outline SOT-23 surface mount package  
using poprietary SuperSOTTM-3 design for superior thermal  
and electrical capabilities.  
cards, and other  
switching, and low in-line power loss are needed in a very  
small outline surface mount package.  
battery powered circuits where fast  
High density cell design for extremely low RDS(ON)  
.
Exceptional on-resistance and maximum DC current  
capability.  
_______________________________________________________________________________  
D
S
G
Absolute Maximum Ratings  
TA = 25°C unless otherwise noted  
Symbol  
VDSS  
VGSS  
ID  
Parameter  
NDS331N  
Units  
Drain-Source Voltage  
20  
8
V
V
A
Gate-Source Voltage - Continuous  
Maximum Drain Current - Continuous  
- Pulsed  
(Note 1a)  
1.3  
10  
Maximum Power Dissipation  
(Note 1a)  
(Note 1b)  
0.5  
W
PD  
0.46  
Operating and Storage Temperature Range  
-55 to 150  
°C  
TJ,TSTG  
THERMAL CHARACTERISTICS  
Thermal Resistance, Junction-to-Ambient  
250  
75  
°C/W  
°C/W  
R
R
JA  
JC  
q
q
(Note 1a)  
(Note 1)  
Thermal Resistance, Junction-to-Case  
© 1997 Fairchild Semiconductor Corporation  
NDS331N Rev.E  

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