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NCV303LSN15T1G PDF预览

NCV303LSN15T1G

更新时间: 2024-11-20 03:56:03
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
26页 195K
描述
Voltage Detector Series with Programmable Delay

NCV303LSN15T1G 数据手册

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NCP302, NCP303  
Voltage Detector Series  
with Programmable Delay  
The NCP302 and NCP303 series are second generation ultra−low  
current voltage detectors that contain a programmable time delay  
generator. These devices are specifically designed for use as reset  
controllers in portable microprocessor based systems where extended  
battery life is paramount.  
Each series features a highly accurate undervoltage detector with  
hysteresis and an externally programmable time delay generator. This  
combination of features prevents erratic system reset operation.  
The NCP302 series consists of complementary output devices that  
are available with either an active high or active low reset. The  
NCP303 series has an open drain N−Channel output with an active low  
reset output.  
http://onsemi.com  
MARKING  
DIAGRAM  
5
1
TSOP−5/  
SOT23−5  
CASE 483  
xxx AYWG  
5
G
1
xxx  
= Specific Device Code  
= Assembly Location  
= Year  
= Work Week  
= Pb−Free Package  
Features  
A
Y
W
G
Quiescent Current of 0.5 mA Typical  
High Accuracy Undervoltage Threshold of 2.0%  
Externally Programmable Time Delay Generator  
Wide Operating Voltage Range of 0.8 V to 10 V  
Complementary or Open Drain Output  
Active Low or Active High Reset  
(Note: Microdot may be in either location)  
PIN CONNECTIONS  
Reset  
Output  
Specified Over the −40°C to +125°C Temperature Range  
(Except for Voltage Options from 0.9 to 1.1 V)  
Pb−Free Packages are Available  
1
2
3
5
C
D
Input  
4
N.C.  
Ground  
Typical Applications  
(Top View)  
Microprocessor Reset Controller  
Low Battery Detection  
ORDERING INFORMATION  
See detailed ordering and shipping information in the ordering  
information section on page 22 of this data sheet.  
Power Fail Indicator  
Battery Backup Detection  
NCP303LSNxxT1  
NCP302xSNxxT1  
Open Drain Output Configuration  
Complementary Output Configuration  
2
Input  
2
Input  
1
Reset Output  
R
R
D
D
1
Reset  
Output  
*
V
ref  
V
ref  
3
GND  
5
C
3
GND  
5
C
D
D
* Inverter for active low devices.  
* Buffer for active high devices.  
This device contains 28 active transistors.  
Figure 1. Representative Block Diagrams  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
May, 2006 − Rev. 19  
NCP302/D  

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