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NCP1362AADR2G PDF预览

NCP1362AADR2G

更新时间: 2024-09-20 02:52:51
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
30页 639K
描述
Primary Side PWM Controller for Low Power Offline SMPS

NCP1362AADR2G 数据手册

 浏览型号NCP1362AADR2G的Datasheet PDF文件第2页浏览型号NCP1362AADR2G的Datasheet PDF文件第3页浏览型号NCP1362AADR2G的Datasheet PDF文件第4页浏览型号NCP1362AADR2G的Datasheet PDF文件第5页浏览型号NCP1362AADR2G的Datasheet PDF文件第6页浏览型号NCP1362AADR2G的Datasheet PDF文件第7页 
Primary Side PWM  
Controller for Low Power  
Offline SMPS  
NCP1362  
The NCP1362 offers a new solution targeting output power levels  
from a few watts up to 50 W in a universalmains flyback application.  
Thanks to a Novel Method this new controller saves the secondary  
feedback circuitry for Constant Voltage and Constant Current  
regulation, achieving excellent line and load regulation without  
traditional opto coupler and TL431 voltage reference.  
The NCP1362 operates in valley lockout quasiresonant peak  
current mode control mode at high load to provide high efficiency.  
When the power on the secondary side starts to diminish, the  
controller automatically adjusts the dutycycle then at lower load the  
controller enters in pulse frequency modulation at fixed peak current  
with a valley switching detection. This technique allows keeping the  
output regulation with tiny dummy load. Valley lockout at the first 4  
valleys prevent valley jumping operation and then a valley switching  
at lower load provides high efficiency.  
www.onsemi.com  
8
1
SOIC8  
CASE 751AZ  
MARKING DIAGRAM  
8
P1362yy  
ALYW  
G
1
Features  
Constant Voltage PrimarySide Regulation < 5%  
Constant Current PrimarySide Regulation < 5%  
IC (PbFree)  
P1362yy = Specific Device Code  
(See page 28)  
LFF and BO Feature on a Dedicated Pin:  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
BO Detection  
LFF for CC Regulation Improvement  
QuasiResonant with Valley Switching Operation  
Optimized Light Load Efficiency and Standby Performance  
Maximum Frequency Clamp (No Clamp, 80, 110 and 140 kHz)  
Cycle by Cycle Peak Current Limit  
PINOUT DIAGRAM  
Output Voltage Under Voltage and Over Voltage Protection  
1
(UVP or OVP)  
Vs/ZCD  
BO/LFF  
VCC  
GND  
COMP  
Fault  
CS  
Secondary Diode or Winding ShortCircuit Protection  
Wide Operation V Range (up to 28 V)  
CC  
DRV  
Low Startup Current  
(Top View)  
CS & V /ZCD Pin Short and Open Protection  
S
Internal Temperature Shutdown  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 28 of  
this data sheet.  
Internal and Fixed Frequency Jittering for Better EMI Signature  
Dual Frozen Peak Current to Both Optimize Light Load Efficiency  
(10% Load) and Standby Performance (Noload)  
Fault Input for Severe Fault Conditions, NTC Compatible for OTP  
These are PbFree Devices  
Applications  
Low Power acdc Adapters for Routers and SetTop Box  
Low Power acdc Adapters for Chargers  
© Semiconductor Components Industries, LLC, 2019  
1
Publication Order Number:  
July, 2020 Rev. 2  
NCP1362/D  

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