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NC7NP14K8X_NL PDF预览

NC7NP14K8X_NL

更新时间: 2024-09-25 20:04:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路
页数 文件大小 规格书
11页 718K
描述
Inverter, P Series, 3-Func, 1-Input, CMOS, PDSO8, 3.10 MM, LEAD FREE, MO-187CA, US-8

NC7NP14K8X_NL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:VSSOP,针数:8
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61系列:P
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:2.3 mm逻辑集成电路类型:INVERTER
功能数量:3输入次数:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH传播延迟(tpd):46.3 ns
认证状态:Not Qualified座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.9 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:2 mmBase Number Matches:1

NC7NP14K8X_NL 数据手册

 浏览型号NC7NP14K8X_NL的Datasheet PDF文件第2页浏览型号NC7NP14K8X_NL的Datasheet PDF文件第3页浏览型号NC7NP14K8X_NL的Datasheet PDF文件第4页浏览型号NC7NP14K8X_NL的Datasheet PDF文件第5页浏览型号NC7NP14K8X_NL的Datasheet PDF文件第6页浏览型号NC7NP14K8X_NL的Datasheet PDF文件第7页 
September 2008  
NC7NP14  
TinyLogic® ULP Triple Inverter with Schmitt Trigger Input  
Features  
General Description  
Space saving US8 package  
The NC7NP14 is a triple inverter with Schmitt trigger  
input from Fairchild’s Ultra Low Power (ULP) Series of  
TinyLogic . Ideal for applications where battery life is  
Ultra small MicroPak™ package  
®
0.9V to 3.6V V supply operation  
CC  
critical, this product is designed for ultra low power con-  
3.6V overvoltage tolerant I/O’s at V from 0.9V  
CC  
sumption within the V operating range of 0.9V to 3.6V  
CC  
to 3.6V  
V
.
CC  
Power-Off high impedance inputs and outputs  
The internal circuit is composed of a minimum of inverter  
stages, including the output buffer, to enable ultra low  
static and dynamic power.  
Static Drive (I /I ):  
OH OL  
2.6mꢀ ꢁ 3.00V V  
2.1mꢀ ꢁ 2.30V V  
1.5mꢀ ꢁ 1.65V V  
1.0mꢀ ꢁ 1.40V V  
0.5mꢀ ꢁ 1.10V V  
CC  
CC  
CC  
CC  
CC  
The NC7NP14 is designed for optimized power and  
speed, and is fabricated with an advanced CMOS tech-  
nology to achieve high speed, low noise operation while  
maintaining extremely low CMOS power dissipation.  
20ꢂꢀ ꢁ 0.9V V  
CC  
Low noise switching using design techniques of  
Quiet Series™ noise/EMI reduction circuitry  
Ultra low dynamic power  
Ordering Information  
Order  
Number  
Package  
Number  
Product Code  
Top Mark  
Package Description  
Supplied As  
NC7NP14K8X  
NC7NP14L8X  
MꢀB08ꢀ  
NP14  
8-Lead US8, JEDEC MO-187,  
Variation Cꢀ 3.1mm Wide  
3k Units on Tape and  
Reel  
MꢀC08ꢀ  
X6  
8-Lead MicroPak, 1.6mm Wide  
5k Units on Tape and  
Reel  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.  
ꢀll packages are lead free per JEDEC: J-STD-020B standard.  
Battery Life vs. V Supply Voltage  
CC  
700  
600  
TinyLogic ULP and ULP-ꢀ with up to 50% less power consumption can  
extend your battery life significantly.  
ULP (SP)  
500  
Battery Life  
(Days)  
400  
300  
200  
100  
0
Battery Life = (V  
x I  
x 0.9) / (P ) / 24hrs/day  
device  
battery  
battery  
2
Where, P  
= (I  
x V ) + (C + C ) x V  
x f  
device  
CC  
CC  
PD  
L
CC  
ULP-A (SV)  
UHS (SZ)  
ꢀssumes ideal 3.6V Lithium Ion battery with current rating of 900mꢀH  
and derated 90% and device frequency at 10MHz, with C = 15pF load.  
L
0.9 1.2 1.5 1.8  
2.5 3.3 5.0  
VCC Supply Voltage  
©2005 Fairchild Semiconductor Corporation  
NC7NP14 Rev. 1.0.0  
www.fairchildsemi.com  

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