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NBXDBA015

更新时间： 2024-11-20 05:51:59

品牌	Logo	应用领域
安森美 - ONSEMI		振荡器时钟
页数	文件大小	规格书
6页	122K
描述
Clock Oscillator

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中文翻译

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数据手册

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NBXDBA015 数据手册

NBXDBA015, NBXDBB015

3.3 V, 200.0 MHz/206.9 MHz

Dual Frequency LVPECL

Clock Oscillator

The NBXDBA015/NBXDBB015 dual frequency crystal oscillator

(XO) is designed to meet today’s requirements for 3.3 V LVPECL

clock generation applications. The device uses a high Q fundamental

crystal and Phase Lock Loop (PLL) multiplier to provide selectable

200.0 MHz or 206.9 MHz, ultra low jitter and phase noise LVPECL

differential output.

This device is a member of ON Semiconductor’s PureEdget clock

family that provides accurate and precision clock solutions.

Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape

and reel in quantities of 1,000. Frequency stability options available as

either 50 PPM NBXDBA015 or 20 PPM NBXDBB015*.

http://onsemi.com

6 PIN CLCC

LN SUFFIX

CASE 848AB

MARKING DIAGRAMS

NBXDBB015

200.0/206.9

AWLYYWW

NBXDBA015

200.0/206.9

AWLYYWW

Features

• LVPECL Differential Output

• Uses High Q Fundamental Mode Crystal and PLL Multiplier

• Ultra Low Jitter and Phase Noise − 0.4 ps (12 kHz − 20 MHz)

• Selectable Output Frequency − 200.0 MHz (default)/206.9 MHz

• Hermetically Sealed Ceramic SMD Package

• RoHS Compliant

NBXDBA015 = NBXDBA015 ( 50 PPM)

NBXDBB015 = NBXDBB015 ( 20 PPM)*

200.0/206.9 = Output Frequency (MHz)

= Assembly Location

= Wafer Lot

= Year

• Operating Range 3.3 V 10%

= Work Week

• Total Frequency Stability − 20 PPM* or 5O PPM

Applications

ORDERING INFORMATION

• High−End Servers

• Basestations

• General Purpose Clock Generation and Margining

Device

Package

Shipping†

NBXDBB015LN1TAG*

NBXDBA015LN1TAG

NBXDBA015LNHTAG

CLCC−6

(Pb−Free) Tape & Reel

1000/

CLCC−6 1000/

(Pb−Free) Tape & Reel

CLCC−6 100/

(Pb−Free) Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

CLK CLK

* Please contact sales office for availability

PLL

Clock

Multiplier

Crystal

FSEL

GND

Figure 1. Simplified Logic Diagram

Semiconductor Components Industries, LLC, 2009

Publication Order Number:

March, 2009 − Rev. 3

NBXDBA015/D

12 3 4 5 6

中文翻译

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