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NANDB0R3N0AZQA5F PDF预览

NANDB0R3N0AZQA5F

更新时间: 2024-11-02 18:32:39
品牌 Logo 应用领域
恒忆 - NUMONYX 动态存储器内存集成电路
页数 文件大小 规格书
52页 1126K
描述
Memory Circuit, Flash+SDRAM, PBGA152,

NANDB0R3N0AZQA5F 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:FBGA, BGA152,21X21,25Reach Compliance Code:unknown
风险等级:5.69JESD-30 代码:S-PBGA-B152
内存集成电路类型:MEMORY CIRCUIT混合内存类型:FLASH+SDRAM
端子数量:152最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA152,21X21,25
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
电源:1.8 V认证状态:Not Qualified
子类别:Other Memory ICs标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:OTHER
端子形式:BALL端子节距:0.635 mm
端子位置:BOTTOMBase Number Matches:1

NANDB0R3N0AZQA5F 数据手册

 浏览型号NANDB0R3N0AZQA5F的Datasheet PDF文件第2页浏览型号NANDB0R3N0AZQA5F的Datasheet PDF文件第3页浏览型号NANDB0R3N0AZQA5F的Datasheet PDF文件第4页浏览型号NANDB0R3N0AZQA5F的Datasheet PDF文件第5页浏览型号NANDB0R3N0AZQA5F的Datasheet PDF文件第6页浏览型号NANDB0R3N0AZQA5F的Datasheet PDF文件第7页 
NANDxxxxNx  
Large page NAND flash memory and  
low power SDRAM, 1.8/2.6 V MCP and PoP  
Features  
FBGA  
n
MCP (multichip package) and PoP (package  
on package)  
TFBGA107 10.5 × 13 × 1.2 mm  
TFBGA137 10.5 x 13 x 1.2 mm  
LFBGA137 10.5 x 13 x 1.4 mm  
TFBGA149 10 × 13.5 × 1.2 mm  
VFBGA160 15 x 15 x 1 mm  
– NAND flash memory  
– 1-, 2-, 4-, 2x2-Gbit large page size NAND  
flash memory  
– 256-, 512-, 2x512-, 128+256/512-Mbit or  
1-Gbit (x16/x32) SDR/DDR LPSDRAM  
FBGA  
n
n
Temperature range: -30 up to 85 °C  
Supply voltage  
– NAND flash: V  
– LPSDRAM: V  
= 1.7-1.95 V or 2.5-3.6 V  
DDF  
VFBGA152 14 x 14 x 0.9 mm  
TFBGA152 14×14 × 1.1 mm  
TFBGA152 14 × 14 × 1.2 mm  
TFBGA128 12 x 12 x 1.1 mm  
= V  
= 1.7-1.95 V  
DDQD  
DDD  
n
n
Electronic signature  
®
ECOPACK packages  
Single or double data rate LPSDRAM  
Flash memory  
n
n
n
n
n
n
n
Interface: x16/32 bus width  
n
n
n
n
Nand interface  
– x8 or x16 bus width  
Deep power-down mode  
– Multiplexed address/data  
Page size  
1.8 V LVCMOS interface  
Quad internal banks controlled by BA0, BA1  
Wrap sequence: sequential/interleaved  
Automatic and controlled precharge  
Auto refresh and self refresh  
– x8 device: (2048 + 64 spare) bytes  
– x16 device: (1024 + 32 spare) words  
Block size  
– x8 device: (128K + 4K spare) bytes  
– x16 device: (64K + 2K spare) words  
– 8192 or 4096 (for 128 Mbits) refresh  
cycles/64 ms  
Page read/program  
– Programmable partial array self refresh  
– Auto temperature compensated self refresh  
– Random access: 25 µs (max)  
– Sequential access: 25/30 ns (min)  
– Page program time: 200 µs (typ)  
Table 1.  
Device summary  
NANDxxxxNx  
n
n
n
n
n
Copy back program mode  
Fast block erase: 1.5/2 ms (typ)  
Chip Enable ‘don’t care’  
Status register  
NANDA0R3N0  
NANDA9R4Nx  
NANDBAR3Nx  
NANDB9R3N0  
NANDA8R3N0  
NANDA9R3Nx  
NANDA9WxN1 NANDB0R3N0  
NANDBAR4Nx  
NANDB9R4Nx  
NANDB1R3N0  
NANDC9R4N0  
Data integrity  
NANDBAW4N1 NANDCAW4N1 NANDCBR4N3  
NANDC3R4N5 NANDD3R4N5 NANDDBR3N5  
– 100 000 program/erase cycles  
– 10 years data retention  
October 2008  
Rev 12  
1/52  
www.numonyx.com  
1

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