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NAND08GW3C2BZL1F PDF预览

NAND08GW3C2BZL1F

更新时间: 2024-10-27 03:23:39
品牌 Logo 应用领域
恒忆 - NUMONYX 闪存内存集成电路
页数 文件大小 规格书
60页 1134K
描述
8 or 16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory

NAND08GW3C2BZL1F 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LGA
包装说明:12 X 17 MM, 0.65 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, LGA-52针数:52
Reach Compliance Code:unknownECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51风险等级:5.78
最长访问时间:25 ns命令用户界面:YES
数据轮询:NOJESD-30 代码:R-PBGA-B52
长度:17 mm内存密度:8589934592 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1部门数/规模:4K
端子数量:52字数:1073741824 words
字数代码:1000000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1GX8封装主体材料:PLASTIC/EPOXY
封装代码:VBGA封装等效代码:LGA52(UNSPEC)
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE
页面大小:2K words并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/3.3 V
编程电压:3 V认证状态:Not Qualified
就绪/忙碌:YES座面最大高度:0.65 mm
部门规模:256K最大待机电流:0.00005 A
子类别:Flash Memories最大压摆率:0.03 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
切换位:NO类型:NAND TYPE
宽度:12 mmBase Number Matches:1

NAND08GW3C2BZL1F 数据手册

 浏览型号NAND08GW3C2BZL1F的Datasheet PDF文件第2页浏览型号NAND08GW3C2BZL1F的Datasheet PDF文件第3页浏览型号NAND08GW3C2BZL1F的Datasheet PDF文件第4页浏览型号NAND08GW3C2BZL1F的Datasheet PDF文件第5页浏览型号NAND08GW3C2BZL1F的Datasheet PDF文件第6页浏览型号NAND08GW3C2BZL1F的Datasheet PDF文件第7页 
NAND08GW3C2B  
NAND16GW3C4B  
8 or 16 Gbit, 2112 byte page,  
3 V supply, multilevel, multiplane, NAND Flash memory  
Target Specification  
Features  
High density multilevel cell (MLC) Flash  
memory  
– Up to 16 Gbit memory array  
– Up to 512 Mbit spare area  
– Cost-effective solutions for mass storage  
applications  
NAND interface  
TSOP48 12 x 20 mm (N)  
– x8 bus width  
– Multiplexed address/data  
Supply voltage: V = 2.7 to 3.6 V  
DD  
Page size: (2048 + 64 spare) bytes  
Block size: (256K + 8K spare) bytes  
LGA52 12 x 17 mm (N)  
Multiplane architecture  
– Array split into two independent planes  
– Program/erase operations can be  
Serial number option  
performed on both planes at the same time  
Chip enable ‘don’t care’  
Data protection  
Memory cell array:  
(2 K + 64 ) bytes x 128 pages x 4096 blocks  
– Hardware program/erase locked during  
power transitions  
Page read/program  
– Random access: 60 µs (max)  
– Sequential access: 25 ns (min)  
– Page program operation time: 800 µs (typ)  
Development tools  
– Error correction code models  
– Bad block management and wear leveling  
algorithm  
Multipage program time (2 pages): 800 µs (typ)  
– HW simulation models  
Copy-back program  
– Fast page copy  
Data integrity  
– 10,000 program/erase cycles (with ECC)  
Fast block erase  
– 10 years data retention  
– Block erase time: 2.5 ms (typ)  
®
ECOPACK packages available  
Multiblock erase time (2 blocks): 2.5 ms (typ)  
Status register  
Electronic signature  
March 2008  
Rev 2  
1/60  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  
www.numonyx.com  
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