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NAND02GR4B2CZB1 PDF预览

NAND02GR4B2CZB1

更新时间: 2024-11-15 04:57:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存存储内存集成电路
页数 文件大小 规格书
64页 633K
描述
1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory

NAND02GR4B2CZB1 技术参数

是否Rohs认证:不符合生命周期:Transferred
零件包装代码:BGA包装说明:9.50 X 12 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TFBGA-63
针数:63Reach Compliance Code:compliant
ECCN代码:3A991.B.1.AHTS代码:8542.32.00.51
风险等级:5.24Is Samacsys:N
最长访问时间:35 nsJESD-30 代码:R-PBGA-B63
JESD-609代码:e0长度:12 mm
内存密度:2147483648 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:63字数:134217728 words
字数代码:128000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED编程电压:1.8 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED类型:NAND TYPE
宽度:9.5 mmBase Number Matches:1

NAND02GR4B2CZB1 数据手册

 浏览型号NAND02GR4B2CZB1的Datasheet PDF文件第2页浏览型号NAND02GR4B2CZB1的Datasheet PDF文件第3页浏览型号NAND02GR4B2CZB1的Datasheet PDF文件第4页浏览型号NAND02GR4B2CZB1的Datasheet PDF文件第5页浏览型号NAND02GR4B2CZB1的Datasheet PDF文件第6页浏览型号NAND02GR4B2CZB1的Datasheet PDF文件第7页 
NAND01G-B  
NAND02G-B  
1 Gbit, 2 Gbit,  
2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory  
Feature summary  
High Density NAND Flash memories  
Up to 2 Gbit memory array  
Up to 64Mbit spare area  
Cost effective solutions for mass  
storage applications  
NAND interface  
x8 or x16 bus width  
TSOP48 12 x 20mm  
Multiplexed Address/ Data  
Pinout compatibility for all densities  
FBGA  
Supply voltage  
1.8V device: VDD = 1.7 to 1.95V  
3.0V device: VDD = 2.7 to 3.6V  
VFBGA63 9.5 x 12 x 1mm  
TFBGA63 9.5 x 12 x 1.2mm  
Page size  
x8 device: (2048 + 64 spare) Bytes  
x16 device: (1024 + 32 spare) Words  
Serial Number option  
Data protection  
Block size  
x8 device: (128K + 4K spare) Bytes  
x16 device: (64K + 2K spare) Words  
Hardware and Software Block Locking  
Hardware Program/Erase locked during  
Power transitions  
Page Read/Program  
Random access: 25µs (max)  
Sequential access: 50ns (min)  
Page program time: 300µs (typ)  
Data integrity  
100,000 Program/Erase cycles  
10 years Data Retention  
Copy Back Program mode  
ECOPACK® packages  
Fast page copy without external  
buffering  
Development tools  
Error Correction Code software and  
hardware models  
Cache Program and Cache Read modes  
Internal Cache Register to improve the  
program and read throughputs  
Bad Blocks Management and Wear  
Leveling algorithms  
Fast Block Erase  
File System OS Native reference  
software  
Block erase time: 2ms (typ)  
Status Register  
Electronic Signature  
Chip Enable ‘don’t care’  
Hardware simulation models  
for simple interface with microcontroller  
February 2006  
Rev 4.0  
1/64  
www.st.com  
2

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