生命周期: | Obsolete | 包装说明: | TSSOP, |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.36 | Is Samacsys: | N |
系列: | LV/LV-A/LVX/H | JESD-30 代码: | R-PDSO-G14 |
长度: | 5 mm | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | AND GATE | 功能数量: | 4 |
输入次数: | 2 | 端子数量: | 14 |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | TSSOP |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH |
传播延迟(tpd): | 19 ns | 认证状态: | Not Qualified |
座面最大高度: | 1.1 mm | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 1 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子形式: | GULL WING |
端子节距: | 0.65 mm | 端子位置: | DUAL |
宽度: | 4.4 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
N74LV08PWDH-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT AND GATE, PDSO14, Gate | |
N74LV08PW-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, QUAD 2-INPUT AND GATE, PDSO14, Gate | |
N74LV107D | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV107DB | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV107DB-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV107D-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV107N | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV107PWDH-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV107PW-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
N74LV10D | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14, Gate |