N74F8965A-T

更新时间： 2024-11-24 13:11:59

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
11页	121K
描述
IC F/FAST SERIES, 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PQCC44, PLASTIC, LCC-44, Bus Driver/Transceiver

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N74F8965A-T 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	其他特性：	BTL PORT STANDARD INPUTS & OPEN COLLECTOR OUTPUTS
系列：	F/FAST	JESD-30 代码：	S-PQCC-J44
长度：	16.5862 mm	负载电容（CL）：	30 pF
逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER	位数：	9
功能数量：	1	端口数量：	2
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		输出特性：	OPEN-COLLECTOR/3-STATE
输出极性：	INVERTED	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	最大电源电流（ICC）：	145 mA
传播延迟（tpd）：	9.5 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	16.5862 mm	Base Number Matches：	1

N74F8965A-T 数据手册

Philips Semiconductors FAST Products

Product specification

9-Bit address/data Futurebus transceiver, ADT

74F8965/74F8966

FEATURES

• 9–bit transceiver (both directions)

• Drives heavily loaded backplanes with

equivalent load impedances down to

10 ohms

BTL offers low power consumption, low

ground bounce, EMI and crosstalk, low

capacitive loading, superior noise margin and

low propagation delays. This results in a high

bandwidth, reliable backplane.

• Guaranteed skew of less than 2ns

DESCRIPTION

The 74F8965 and 74F8966 are 9–bit

bidirectional latchable transceivers and are

intended to provide the electrical interface to

a high performance wired–OR bus. The B

port inverting drivers are low–capacitance

open collector with controlled ramp and are

designed to sink 100mA from 2 volts. The B

port inverting receivers have a precision band

gap references for improved noise margins.

The 74F8965 and 74F8966 A ports have TTL

3–state drivers and TTL receivers.

• High drive (100mA) open collector

drivers on B port

The B ports have standard BTL I/O with

• Reduced voltage swing (1V to 2V)

produces less noise and reduces

power consumption

100mA current sink capability. The B–to–A

path is a simple inverted buffered path. When

going from A–to–B the user may choose be-

tween a buffered path or a latching function.

• High speed operation enhances

performance of backplane buses and

facilitates incident wave switching

The 74F8966 also has an idle arbitrator/multi-

ple competitors output. The IAMC output

compares, using a wired–OR configuration,

the data on the bus to the latched data pres-

ented to the bus. If the bus data matches the

data presented by the 74F8966 then IAMC is

high. If the data doesn’t match then IAMC

goes low.

The B port interfaces to ’Backplane

Transceiver Logic’ (BTL). BTL features a

reduced (1V to 2V) voltage swing for lower

power consumption and a series diode on

the drivers to reduce capacitive loading.

• Compatible with IEEE 896 futurebus

standards and IEEE 1194 BTL stan-

dard

• Built–in precision band–gap reference

provides accurate receiver thresholds

and improved noise immunity

Incident wave switching is employed, there-

fore BTL propagation delays are short. Al-

though the voltage swing is much less for

BTL, so is its receiver threshold region,

therefore noise margins are excellent.

• Controlled output ramp and multiple

GND pins minimize ground bounce

• Glitch–free power up/power down

operation

TYPE

TYPICAL PROPAGATION DELAY

TYPICAL SUPPLY CURRENT( TOTAL)

74F8965

74F8966

3.5ns

80mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

= 5V ±10%, T

= 0°C to +70°C

amb

44–pin PLCC

N74F8965A, N74F8966A

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

PINS

DESCRIPTION

A0 – A8

B0 – B8

TTL data inputs

1.0/0.033

5.0/0.167

20µA/20µA

Data inputs with threshold circuitry

Output enable inputs

100µA/100µA

OEA, OEB0, OEB1

1.0/0.167

20µA/100µA

Latch select (active low) (’F8965)

Idle arbitration request (active low) (’F8965)

Latch enable input (active low)

1.0/0.167

150/40

20µA/100µA

3mA/24mA

OC/100mA

IAREQ

A0 – A8

B0 – B8

3–state TTL outputs

Open collector BTL outputs

OC/166.7

Idle arbitration/multiple competitors output (’F8966)

IAMC

OC/80

OC/48mA

Notes to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

2. OC = Open collector.

December 19, 1990

853 1526 01320

12 3 4 5 6 7...11

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与N74F8965A-T相关器件

型号	品牌	获取价格	描述	数据表
N74F8966A	NXP	获取价格	9-Bit address/data Futurebus transceiver, ADT
N74F8966AB	PHILIPS	获取价格	Registered Bus Transceiver, 1-Func, 9-Bit, Inverted Output, TTL, PQCC44
N74F899A	PHILIPS	获取价格	Registered Bus Transceiver, 1-Func, 8-Bit, True Output, TTL, PQCC28
N74F899A	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 9-Bit, True Output, TTL, PDSO28
N74F899A-T	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 9-Bit, True Output, TTL, PDSO28
N74F899N	PHILIPS	获取价格	Registered Bus Transceiver, 1-Func, 8-Bit, True Output, TTL, PDIP28
N74F899N	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 9-Bit, True Output, TTL, PDIP28
N74H00A	NXP	获取价格	NAND Gate, TTL/H/L Series, 4-Func, 2-Input, TTL, PDIP14
N74H00F	PHILIPS	获取价格	NAND Gate, TTL, CDIP14
N74H00FB	PHILIPS	获取价格	NAND Gate, TTL, CDIP14

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