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N74F8961A

更新时间： 2024-11-23 22:54:35
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路光电二极管
页数 文件大小 规格书
11页 198K
描述
Octal latched bidirectional Futurebus transceivers 3-State open-collector

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中文翻译

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N74F8961A 技术参数

是否Rohs认证： 不符合生命周期：End Of Life
零件包装代码：QLCC包装说明：PLASTIC, LCC-28
针数：28Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.66
其他特性：COMPATIBLE IEEE FUTUREBUS STANDARDS; BTL PORT STANDARD INPUTS AND OPEN COLLECTOR OUTPUTS系列：F/FAST
JESD-30 代码：S-PQCC-J28长度：11.5062 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：28
最高工作温度：70 °C最低工作温度：
输出特性：OPEN-COLLECTOR/3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
最大电源电流（ICC）：145 mA传播延迟（tpd）：9 ns
认证状态：Not Qualified座面最大高度：4.57 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：11.5062 mm
Base Number Matches：1

N74F8961A 数据手册

 浏览型号N74F8961A的Datasheet PDF文件第2页浏览型号N74F8961A的Datasheet PDF文件第3页浏览型号N74F8961A的Datasheet PDF文件第4页浏览型号N74F8961A的Datasheet PDF文件第5页浏览型号N74F8961A的Datasheet PDF文件第6页浏览型号N74F8961A的Datasheet PDF文件第7页 
Philips Semiconductors FAST Products  
Product specification  
Octal latched bidirectional Futurebus transceivers  
(3-State + open-collector)  
74F8960/74F8961  
voltage swing is much less for BTL, so is its  
receiver threshold region, therefore noise  
margins are excellent.  
FEATURES  
• Octal latched transceiver  
DESCRIPTION  
The 74F8960 and 74F8961 are octal  
bidirectional latched transceivers and are  
intended to provide the electrical interface to  
a high performance wired–OR bus. The B  
port inverting drivers are low–capacitance  
open collector with controlled ramp and are  
designed to sink 100mA from 2 volts. The B  
port inverting receivers have a 100 mV  
threshold region and a 4ns glitch filter.  
• Drives heavily loaded backplanes with  
equivalent load impedances down to 10Ω  
BTL offers low power consumption, low  
ground bounce, EMI and crosstalk, low  
capacitive loading, superior noise margin and  
low propagation delays. This results in a high  
bandwidth, reliable backplane.  
• High drive (100mA) open collector drivers  
on B port  
• Reduced voltage swing (1 volt) produces  
The 74F8960 and 74F8961 A ports have TTL  
3–state drivers and TTL receivers with a latch  
function. A separate High–level control input  
(VX) is provided to limit the A side output  
level to a given voltage level (such as 3.3V).  
For 5.0V systems, VX is simply tied to VCC.  
less noise and reduces power consumption  
• High speed operation enhances  
performance of backplane buses and  
facilitates incident wave switching  
The B port interfaces to ‘Backplane  
Transceiver Logic’ (BTL). BTL features a  
reduced (1V to 2V) voltage swing for lower  
power consumption and a series diode on  
the drivers to reduce capacitive loading.  
• Compatible with IEEE futurebus standards  
The 74F8961 is the non–inverting version of  
74F8960.  
• Built-in precision band-gap reference  
provides accurate receiver thresholds and  
improved noise immunity  
Incident switching is employed, therefore BTL  
propagation delays are short. Although the  
• Controlled output ramp and multiple GND  
pins minimize ground bounce  
• Glitch-free power up/down operation  
TYPE  
TYPICAL PROPAGATION DELAY  
TYPICAL SUPPLY CURRENT( TOTAL)  
74F8960  
74F8961  
6.5ns  
6.5ns  
80mA  
80mA  
ORDERING INFORMATION  
ORDER CODE  
DESCRIPTION  
COMMERCIAL RANGE  
V
CC  
= 5V ±10%, T  
= 0°C to +70°C  
amb  
1
28–pin plastic DIP (300 mil)  
N74F8960N, N748961N  
N74F8960A, N74F8961A  
1
28–pin PLCC  
NOTE: Thermal mounting techiques are recommended.  
INPUT AND OUTPUT LOADING AND FAN OUT TABLE  
74F (U.L.)  
HIGH/LOW  
LOAD VALUE  
HIGH/LOW  
PINS  
DESCRIPTION  
A0 – A8  
B0 – B8  
OEA  
PNP latched inputs  
3.5/0.117  
5.0/0.167  
1.0/0.033  
1.0/0.033  
1.0/0.033  
150/40  
70µA/70µA  
100µA/100µA  
20µA/20µA  
20µA/20µA  
20µA/20µA  
3mA/24mA  
OC/100mA  
Data inputs with threshold circuitry  
A output enable input (active high)  
B output enable inputs (active low)  
Latch enable input (active low)  
3–state outputs  
OEB0, OEB1  
LE  
A0 – A7  
B0 – B7  
Open collector outputs  
OC/166.7  
NOTES:  
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.  
2. OC = Open collector.  
1
December 19, 1990  
853-1120 01322  
1234567...11

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与N74F8961A相关器件

型号 品牌 获取价格 描述 数据表
N74F8961AB ETC

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 		Single 8-bit Bus Transceiver
N74F8961A-T YAGEO

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 		Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO28
N74F8961D YAGEO

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 		Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PQCC28
N74F8961D-T YAGEO

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 		Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PQCC28
N74F8961N ETC

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 		Single 8-bit Bus Transceiver
N74F8961N-B ETC

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 		Single 8-bit Bus Transceiver
N74F8962A NXP

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 		9-Bit latched bidirectional Futurebus transceivers open-collector
N74F8962AB ETC

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 		Single 8-Bit Inverting Bus Transceiver
N74F8962A-T PHILIPS

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 		Registered Bus Transceiver, 1-Func, 8-Bit, Inverted Output, TTL, PQCC44,
N74F8962Y NXP

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 		9-Bit latched bidirectional Futurebus transceivers open-collector

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