N74F807A

更新时间： 2024-09-18 22:15:59

品牌	Logo	应用领域
恩智浦 - NXP		总线驱动器总线收发器逻辑集成电路
页数	文件大小	规格书
8页	73K
描述
Octal shift/count registered transceiver with adder and parity 3.State

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N74F807A 技术参数

生命周期：	Obsolete	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	其他特性：	SHIFT/COUNT REGISTERED TRANSCEIVER WITH ADDER & PARITY
系列：	F/FAST	JESD-30 代码：	S-PQCC-J28
长度：	11.5062 mm	负载电容（CL）：	50 pF
逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER	位数：	8
功能数量：	1	端口数量：	2
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	最大电源电流（ICC）：	210 mA
传播延迟（tpd）：	10 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.5062 mm	Base Number Matches：	1

N74F807A 数据手册

Philips Semiconductors FAST Products

Product specification

Octal shift/count registered transceiver

with adder and parity (3–State)

FAST 74F807

input and the STATOUT output is terminal

count. In this mode the CI/SI/CE input must

be high to enable the count function. The

FEATURES

this device only on the output states.

Both OE pins are enabled low.

• High speed parallel registers with

positive edge–triggered D–type

flip–flops

All operating modes, other than clear,

3–State, and the two hold modes re-

quire the rising edge of the clock. All

setup and hold times must be observed

for proper functioning.

4. Count w/count enable (hold) –– same as

above except no incrementing occurs.

• High speed full adder

• 8–bit parity generator

• High impedance PNP inputs for light

bus loading

5. Count wo/count enable –– same as num-

ber 3 except the CI/SI/CE input has no con-

trol over counting or holding.

6. Shift –– The CI/SI/CE input now becomes

the serial input and the STATOUT output

becomes the serial output. In this mode the

CI/SI/CE input is shifted into the Q0 register,

Q0 into the Q1 register etc. The Q7 register

is shifted into the STATOUT.

Data on the internal register can be

switched on either the A or B ports for

output.

• Center V_CCand GND pins and con-

trolled output buffers minimize

ground–bounce problems

Depeding on the state of the select in-

puts (S0, S1, S2), and carry in/ serial in/

clock enable (CI/SI/CE), the 74F807 has

nine distinct operating modes:

• 3–State glitch–free power–up and

power–down

7. Load A inputs –– The CI/SI/CE input has

no bearing in either of the load modes. The

STATOUT output becomes the parity out.

The parity out is high for an odd number of

registered bits high, and low for even number

of registered bits high (even parity). In this

mode the An inputs are loaded into the

internal register and output to the B bus. If

OEA = low the internal register would wrap

around and be loaded again.

• Broadside pinout

1. Add mode w/carry in – the CI/SI/CE

input is used as a carry in signal and the

STATOUT output is the carry out signal.

(In add mode the COUT is NOT

registered. This means the carry output

signal appears at the STATOUT output

one clock prior to the related data.). In

this mode, the CI/SI/CE input is added

to the register contents and to the

inputs. (The adder uses only the An

inputs, not the Bn inputs.)

DESCRIPTION

The 74F807 is a registered transceiver

that also has the capability to perform

count, shift, and add functions. It is also

has the capability to generate a parity

bit output. All of this is done within a

28–pin package.

8. Load B inputs –– same as number 7

except the A and B busses are switched.

9. Hold –– Again the CI/SI/CE input is not

used; the STATOUT output is still the parity

out. In this mode either the A bus, B bus or

both can be held with the registered data. No

other operation is performed.

The MR input is an overriding

asynchronous reset which forces the

STATOUT output low as well as the A

and B busses.

2. Add mode wo/carry in –– same as above

except the CI/SI/CE input is not included in

the addition.

The A and B busses have separate OE

inputs (OEA, OEB]. These inputs have

no bearing on the internal functioning of

3. Count w/count enable (count) –– the CI/SI/

CE input is now used as the count enable

TYPE

TYPICAL f

TYPICAL SUPPLY CURRENT (TOTAL)

max

74F807

115MHz

155mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

= 5V ±10%, T

= 0°C to +70°C

amb

28–pin plastic DIP (300 mils)

N74F807N

N74F807D

N74F807A

28–pin SOL

28–pin PLCC

Note to ordering information

1.Thermal mounting techiques are recommended. See SMD Process Applications (page 17) for a discussion of thermal consideration for surface

mounted devices.

June 18, 1991

853–1421 02931

12 3 4 5 6 7 8

中文翻译

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与N74F807A相关器件

型号	品牌	获取价格	描述	数据表
N74F807A-T	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PQCC28
N74F807D	NXP	获取价格	Octal shift/count registered transceiver with adder and parity 3.State
N74F807D	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO28
N74F807DB	ETC	获取价格	Single 8-bit Bus Transceiver
N74F807D-T	NXP	获取价格	IC F/FAST SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO28, SO-28, Bus Driver/Tra
N74F807D-T	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDSO28
N74F807N	NXP	获取价格	Octal shift/count registered transceiver with adder and parity 3.State
N74F807N	YAGEO	获取价格	Registered Bus Transceiver, F/FAST Series, 1-Func, 8-Bit, True Output, TTL, PDIP28
N74F807N-B	ETC	获取价格	Single 8-bit Bus Transceiver
N74F808D	NXP	获取价格	Hex 2-input AND drivers

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