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N64T1618C1BZ-70I PDF预览

N64T1618C1BZ-70I

更新时间: 2024-09-28 19:44:23
品牌 Logo 应用领域
NANOAMP 动态存储器
页数 文件大小 规格书
18页 348K
描述
DRAM

N64T1618C1BZ-70I 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.75
Base Number Matches:1

N64T1618C1BZ-70I 数据手册

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NanoAmp Solutions, Inc.  
1982 Zanker Road, San Jose, CA 95112  
ph: 408-573-8878, FAX: 408-573-8877  
www.nanoamp.com  
N64T1618C1B  
Advance Information  
64Mb Ultra-Low Power Asynchronous CMOS PSRAM  
4M × 16 Bits  
Overview  
Features  
The N64T1618C1B is an integrated memory  
device containing a 64 Mbit Pseudo Static Random  
Access Memory using a self-refresh DRAM array  
organized as 4,194,304 words by 16 bits. It is  
designed to be compatible in operation and  
interface to standard 6T SRAMS. The device is  
designed for low standby and operating current  
and includes a power-down feature to  
automatically enter standby mode. The device  
includes a ZZ input for deep sleep as well as  
several other power saving modes: Partial Array  
Self Refresh mode where data is retained in a  
portion of the array and Temperature  
Compensated Refresh. Both these modes reduce  
standby current drain. The N64T1618C1B can be  
operated in a standard asynchronous mode and  
data can also be read in a 4-word page mode for  
fast access times. The die has separate power  
rails, VccQ and VssQ for the I/O to be run from a  
separate power supply from the device core.  
Table 1: Product Family  
• Dual voltage rails for optimum power & per-  
formance  
Vcc - 1.7V - 1.95V  
VccQ - 1.7V to 2.25V  
VccQ - 2.3V to 2.7V  
VccQ - 2.7V to 3.3V  
• Fast Cycle Times  
T
< 70 ns  
PACC  
ACC  
T
< 25 ns  
• Very low standby current  
I
< 120 µA  
SB  
• Very low operating current  
Icc < 25 mA  
• PASR (Partial Array Self Refresh)  
• TCR (Temperature Compensated Refresh)  
Standby  
Package  
Type  
Operating  
Power  
Current(ISB),  
Max  
Part Number  
I/O Supply  
Speed  
Temperature  
Supply  
1.7 - 1.95V  
2.3 - 2.7V  
2.7 - 3.3V  
-25oC to +85oC  
N64T1618C1BZ  
BGA  
1.70 - 1.95V  
70ns  
120 µA  
Ball Description  
Ball Congiguration  
1
2
3
A0  
4
A1  
5
A2  
6
ZZ  
LB  
OE  
A
B
C
D
E
F
Pin Name  
A -A  
Pin Function  
I/O8  
A3  
A4  
A6  
A7  
I/O0  
UB  
CE  
Address Inputs  
Write Enable Input  
Chip Enable Input  
Deep Sleep Input  
Output Enable Input  
0
21  
I/O9 I/O10 A5  
VSSQ I/O11 A17  
VCCQ I/O12 A21  
I/O14 I/O13 A14  
I/O1 I/O2  
I/O3 VCC  
WE  
CE  
ZZ  
A16 I/O4 VSS  
A15 I/O5 I/O6  
OE  
LB  
Lower Byte Enable Input  
Upper Byte Enable Input  
Data Inputs/Outputs  
I/O15 A19  
A18 A8  
A12  
A9  
A13  
A10  
I/O7  
A20  
WE  
A11  
G
H
UB  
I/O -I/O  
0
15  
48 Pin BGA (top view)  
6 x 8 mm  
V
Power  
CC  
V
Ground  
SS  
V
Power I/O only  
Ground I/O only  
CCQ  
V
SSQ  
Stock No. 23403- Rev A 01/05  
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.  
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