N16D1618LPA
512K x 16Bits x 2Banks Low Power Synchronous DRAM
Description
These N16D1618LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 16 bits. These
products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 1.8V power supply.
• Auto refresh and self refresh.
• All inputs and outputs referenced to the positive edge of the
system clock.
• All pins are compatible with LVCMOS interface.
• 4K refresh cycle / 64ms.
• Data mask function by DQM.
• Internal dual banks operation.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Burst Read Single Write operation.
• Special Function Support.
- PASR(Partial Array Self Refresh)
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
• Deep Power Down Mode.
- Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Table1: Ordering Information
Part No.
Clock Freq.
166 MHz
133 MHz
100 MHz
166 MHz
133 MHz
100 MHz
Temperature
VDD/VDDQ
Interface
Package
N16D1618LPAC2-60I
N16D1618LPAC2-75I
N16D1618LPAC2-10I
N16D1618LPAT2-60I
N16D1618LPAT2-75I
N16D1618LPAT2-10I
60-Ball Green
FBGA
-25°C to 85°C
1.8V/1.8V
LVCMOS
50-Pin Green
TSOPII
1
Enable Semiconductor Corp. reserves the right to change products or specifications without notice.
Ver. A