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MX29F200CTMI-55G PDF预览

MX29F200CTMI-55G

更新时间: 2024-11-08 03:27:11
品牌 Logo 应用领域
旺宏电子 - Macronix 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
44页 435K
描述
2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY

MX29F200CTMI-55G 数据手册

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MX29F200C T/B  
2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY  
FEATURES  
• 5.0V±10% for read, erase and write operation  
• 131072x16/262144x8 switchable  
• Fast access time: 55/70/90ns  
CompatiblewithMX29F200T/Bdevice  
• Lowpowerconsumption  
- 40mA maximum active current@5MHz  
- 1uA typical standby current  
• Command register architecture  
- Byte/Word Programming (9us/11us typical)  
-SectorErase(16K-Bytex1,8K-Bytex2,32K-Bytex1,  
and 64K-Byte x3)  
- Superiorinadvertentwriteprotection  
• Sector protection  
- Hardware method to disable any combination of  
sectors from program or erase operations  
-Temporarysectorunprotectallowscodechangesin  
previously locked sectors  
• Sector protect/chip unprotect for 5V only system  
• 100,000minimumerase/programcycles  
• Latch-up protected to 100mA from -1V to VCC+1V  
• Boot Code Sector Architecture  
- T = Top Boot Sector  
• Auto Erase (chip & sector) and Auto Program  
- Automatically erase any combination of sectors or  
the whole chip with Erase Suspend capability.  
- Automatically program and verify data at specified  
address  
- B = Bottom Boot Sector  
• Low VCC write inhibit is equal to or less than 3.2V  
• Erase suspend/ Erase Resume  
- Suspends an erase operation to read data from, or  
programdatatoasectorthatisnotbeingerased,then  
resume the erase operation.  
• Status Reply  
- Data# Polling & Toggle bit for detection of program  
and erase cycle completion.  
• Ready/Busy#pin(RY/BY#)  
• Hardwareresetpin  
- Resets internal state mechine to the read mode  
• 20 years data retention  
- Provides a hardware method or detecting program  
or erase cycle completion  
• Package type:  
- 44-pin SOP  
• Compatibility with JEDEC standard  
- Pinout and software compatible with single-power  
supply Flash  
- 48-pin TSOP  
- All Pb-free devices are RoHS Compliant  
GENERAL DESCRIPTION  
TheMX29F200CT/Bisa2-megabit, single5VoltFlash  
memoryorganizedas1Mwordx16or2Mbytex8MXIC's  
Flash memories offer the most cost-effective and reli-  
able read/write non-volatile random access memory.  
TheMX29F200CT/Bispackagedin44-pinSOPand48-  
pin TSOP. It is designed to be reprogrammed and  
erasedin-systemorin-standardEPROMprogrammers.  
TTL level control inputs and fixed power supply levels  
duringeraseandprogramming,whilemaintainingmaxi-  
mum EPROM compatibility.  
MXICFlashtechnologyreliablystoresmemorycontents  
evenafter100,000eraseandprogramcycles. TheMXIC  
cell is designed to optimize the erase and programming  
mechanisms. In addition, the combination of advanced  
tunneloxideprocessingandlowinternalelectricfieldsfor  
erase and programming operations produces reliable  
cycling. The MX29F200C T/B uses a 5.0V ±10% VCC  
supply to perform the High Reliability Erase and auto  
Program/Erasealgorithms.  
ThestandardMX29F200CT/Boffersaccesstimeasfast  
as55ns, allowingoperationofhigh-speedmicroproces-  
sorswithoutwaitstates. Toeliminatebuscontention,the  
MX29F200C T/B has separate chip enable (CE#) and  
output enable (OE# ) controls.  
MXIC's Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
MX29F200C T/B uses a command register to manage  
thisfunctionality. Thecommandregisterallowsfor100%  
The highest degree of latch-up protection is achieved  
with MXIC's proprietary non-epi process. Latch-up  
protection is proved for stresses up to 100 milliamps on  
address and data pin from -1V to VCC + 1V.  
P/N:PM1250  
REV. 1.0, DEC. 14, 2005  
1

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