PRELIMINARY
MX29F1615
16M-BIT [2M x8/1M x16] CMOS
SINGLE VOLTAGE FLASH EEPROM
FEATURES
• Software and hardware data protection
• 5V ±10% write and erase
• Pageprogramoperation
- Internal address and data latches for 64 words per
page
- Page programming time: 0.9ms typical
• Low power dissipation
- 30mA typical active current
- 1uA typical standby current
• CMOS and TTL compatible inputs and outputs
• Package Type:
- 42 lead PDIP
• JEDEC-standard EEPROM commands
• Endurance:100 cycles
• Fast access time: 90/100/120ns
• Auto Erase and Auto Program Algorithms
- Automatically erases the whole chip
- Automatically programs and verifies data at
specified addresses
• Status Register feature for detection of
program or erase cycle completion
• Low VCC write inhibit is equal to or less than 3.2V
GENERAL DESCRIPTION
TheMX29F1615isa16-megabitFlashmemoryorganized
as either 1M wordx16 or 2M bytex8. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory. The
MX29F1615 is packaged in 42-pin PDIP. It is designed
to be reprogrammed and in standard EPROM
programmers.
To allow for simple in-system reprogrammability, the
MX29F1615 requireshighinputvoltages(10V)onBYTE/
VPPpinforprogramming. Readingdataoutofthedevice
is similar to reading from an EPROM.
MXIC Flash technology reliably stores memory contents
even after 100 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programming operations produces reliable cycling. The
MX29F1615 uses a 5V ±10% VCC supply to perform the
Auto Erase and Auto Program algorithms.
The standard MX29F1615 offers access times as fast as
90ns,allowing operation of high-speed microprocessors
withoutwait. Toeliminatebuscontention,theMX29F1615
has separate chip enables(CE) and output enable (OE)
control.
MXIC's Flash memories augment EPROM functionality
withelectricalerasureandprogramming. TheMX29F1615
uses a command register to manage this functionality.
The command register allows for 100% TTL level control
inputs and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
REV.1.1, JUN. 15, 2001
P/N: PM0615
1