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MUN5133DW1T1 PDF预览

MUN5133DW1T1

更新时间: 2024-01-01 12:53:31
品牌 Logo 应用领域
安森美 - ONSEMI 晶体晶体管
页数 文件大小 规格书
20页 176K
描述
Dual Bias Resistor Transistors

MUN5133DW1T1 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SC-88包装说明:SMALL OUTLINE, R-PDSO-G6
针数:6Reach Compliance Code:compliant
ECCN代码:EAR99风险等级:0.94
其他特性:BUILT-IN BIAS RESISTOR RATIO IS 0.12最大集电极电流 (IC):0.1 A
集电极-发射极最大电压:50 V配置:SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
最小直流电流增益 (hFE):80JESD-30 代码:R-PDSO-G6
JESD-609代码:e3湿度敏感等级:1
元件数量:2端子数量:6
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260极性/信道类型:PNP
最大功率耗散 (Abs):0.15 W认证状态:Not Qualified
子类别:BIP General Purpose Small Signal表面贴装:YES
端子面层:Tin (Sn)端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:40
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

MUN5133DW1T1 数据手册

 浏览型号MUN5133DW1T1的Datasheet PDF文件第2页浏览型号MUN5133DW1T1的Datasheet PDF文件第3页浏览型号MUN5133DW1T1的Datasheet PDF文件第4页浏览型号MUN5133DW1T1的Datasheet PDF文件第5页浏览型号MUN5133DW1T1的Datasheet PDF文件第6页浏览型号MUN5133DW1T1的Datasheet PDF文件第7页 
MUN5111DW1T1 Series  
Preferred Devices  
Dual Bias Resistor  
Transistors  
PNP Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
http://onsemi.com  
The BRT (Bias Resistor Transistor) contains a single transistor with  
a monolithic bias network consisting of two resistors; a series base  
resistor and a base−emitter resistor. These digital transistors are  
designed to replace a single device and its external resistor bias  
network. The BRT eliminates these individual components by  
integrating them into a single device. In the MUN5111DW1T1 series,  
two BRT devices are housed in the SOT−363 package which is ideal  
for low−power surface mount applications where board space is at a  
premium.  
(3)  
(2)  
(1)  
R
1
R
2
Q
1
Q
2
R
2
R
1
(4)  
(5)  
(6)  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
Available in 8 mm, 7 inch/3000 Unit Tape and Reel  
1
SOT−363  
CASE 419B  
STYLE 1  
MAXIMUM RATINGS  
(T = 25°C unless otherwise noted, common for Q and Q )  
A
1
2
Rating  
Symbol  
Value  
Unit  
Vdc  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
V
50  
−50  
CBO  
CEO  
MARKING DIAGRAM  
V
Vdc  
6
I
C
−100  
mAdc  
d
XX  
THERMAL CHARACTERISTICS  
Characteristic  
(One Junction Heated)  
1
Symbol  
Max  
Unit  
Total Device Dissipation  
P
187 (Note 1.)  
256 (Note 2.)  
1.5 (Note 1.)  
2.0 (Note 2.)  
mW  
XX= Specific Device Code  
D
d
T = 25°C  
= Date Code  
= (See Page 2)  
A
Derate above 25°C  
mW/°C  
°C/W  
Thermal Resistance −  
Junction-to-Ambient  
R
670 (Note 1.)  
490 (Note 2.)  
θ
JA  
DEVICE MARKING INFORMATION  
Characteristic  
(Both Junctions Heated)  
See specific marking information in the device marking table  
on page 2 of this data sheet.  
Symbol  
Max  
Unit  
Total Device Dissipation  
P
250 (Note 1.)  
385 (Note 2.)  
2.0 (Note 1.)  
3.0 (Note 2.)  
mW  
D
T = 25°C  
Preferred devices are recommended choices for future use  
and best overall value.  
A
Derate above 25°C  
mW/°C  
°C/W  
°C/W  
°C  
Thermal Resistance −  
Junction-to-Ambient  
R
493 (Note 1.)  
325 (Note 2.)  
θ
JA  
JL  
Thermal Resistance −  
Junction-to-Lead  
R
188 (Note 1.)  
208 (Note 2.)  
θ
Junction and Storage  
Temperature Range  
T , T  
J
55 to +150  
stg  
1. FR−4 @ Minimum Pad  
2. FR−4 @ 1.0 x 1.0 inch Pad  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
December, 2003 − Rev. 5  
MUN5111DW1T1/D  
 

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