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MUN5130DW1T1G

更新时间: 2024-01-23 00:29:51
品牌 Logo 应用领域
安森美 - ONSEMI 晶体晶体管
页数 文件大小 规格书
20页 148K
描述
Dual Bias Resistor Transistors

MUN5130DW1T1G 数据手册

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MUN5111DW1T1 Series  
Preferred Devices  
Dual Bias Resistor  
Transistors  
PNP Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
http://onsemi.com  
The BRT (Bias Resistor Transistor) contains a single transistor with a  
monolithic bias network consisting of two resistors; a series base resistor  
and a base−emitter resistor. These digital transistors are designed to  
replace a single device and its external resistor bias network. The BRT  
eliminates these individual components by integrating them into a single  
device. In the MUN5111DW1T1 series, two BRT devices are housed in  
the SOT−363 package which is ideal for low−power surface mount  
applications where board space is at a premium.  
(3)  
(2)  
(1)  
R
1
R
2
Q
1
Q
2
R
2
R
1
Features  
(4)  
(5)  
(6)  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
Pb−Free Packages are Available  
1
MAXIMUM RATINGS  
(T = 25°C unless otherwise noted, common for Q and Q )  
A
1
2
SOT−363  
CASE 419B  
STYLE 1  
Rating  
Symbol  
Value  
50  
−50  
−100  
Unit  
Vdc  
Collector-Base Voltage  
V
CBO  
Collector-Emitter Voltage  
Collector Current  
V
Vdc  
CEO  
I
mAdc  
C
THERMAL CHARACTERISTICS  
MARKING DIAGRAM  
Characteristic  
(One Junction Heated)  
Symbol  
Max  
Unit  
6
Total Device Dissipation  
T = 25°C  
A
P
187 (Note 1)  
256 (Note 2)  
mW  
D
xx M G  
1.5 (Note 1) mW/°C  
2.0 (Note 2)  
Derate above 25°C  
G
1
Thermal Resistance,  
Junction-to-Ambient  
R
q
JA  
670 (Note 1) °C/W  
490 (Note 2)  
Characteristic  
(Both Junctions Heated)  
xx = Device Code (Refer to page 2)  
Symbol  
Max  
Unit  
M
= Date Code  
Total Device Dissipation  
P
250 (Note 1)  
385 (Note 2)  
2.0 (Note 1) mW/°C  
3.0 (Note 2)  
mW  
D
G
= Pb−Free Package  
T = 25°C  
A
(Note: Microdot may be in either location)  
Derate above 25°C  
ORDERING INFORMATION  
See detailed ordering and shipping information in the table on  
page 2 of this data sheet.  
Thermal Resistance,  
Junction-to-Ambient  
R
q
JA  
493 (Note 1) °C/W  
325 (Note 2)  
Thermal Resistance,  
Junction-to-Lead  
R
q
JL  
188 (Note 1) °C/W  
208 (Note 2)  
DEVICE MARKING INFORMATION  
Junction and Storage Temperature Range T , T  
55 to +150  
°C  
See specific marking information in the device marking table  
on page 2 of this data sheet.  
J
stg  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
Preferred devices are recommended choices for future use  
and best overall value.  
1. FR−4 @ Minimum Pad  
2. FR−4 @ 1.0 x 1.0 inch Pad  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
September, 2005 − Rev. 6  
MUN5111DW1T1/D  
 

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