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MUN5111T1/D

更新时间： 2024-01-18 20:19:44
品牌 Logo 应用领域
其他 - ETC 晶体晶体管
页数 文件大小 规格书
16页 139K
描述
Bias Resistor Transistor

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中文翻译

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MUN5111T1/D 技术参数

是否无铅：不含铅生命周期：Active
零件包装代码：SC-70包装说明：SMALL OUTLINE, R-PDSO-G3
针数：3Reach Compliance Code：compliant
ECCN代码：EAR99Factory Lead Time：1 week
风险等级：0.51Samacsys Confidence：4
Samacsys Status：ReleasedSamacsys PartID：412151
Samacsys Pin Count：3Samacsys Part Category：Transistor RET PNP
Samacsys Package Category：SOT23 (3-Pin)Samacsys Footprint Name：SC-70 (SOT-323) CASE419-04 ISSUE N
Samacsys Released Date：2018-06-29 12:49:47Is Samacsys：N
其他特性：BUILT-IN BIAS RESISTOR RATIO IS 1最大集电极电流 (IC)：0.1 A
集电极-发射极最大电压：50 V配置：SINGLE WITH BUILT-IN RESISTOR
最小直流电流增益 (hFE)：35JESD-30 代码：R-PDSO-G3
JESD-609代码：e3湿度敏感等级：1
元件数量：1端子数量：3
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260极性/信道类型：PNP
最大功率耗散 (Abs)：0.31 W认证状态：Not Qualified
子类别：BIP General Purpose Small Signal表面贴装：YES
端子面层：Tin (Sn)端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：40
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

MUN5111T1/D 数据手册

 浏览型号MUN5111T1/D的Datasheet PDF文件第2页浏览型号MUN5111T1/D的Datasheet PDF文件第3页浏览型号MUN5111T1/D的Datasheet PDF文件第4页浏览型号MUN5111T1/D的Datasheet PDF文件第5页浏览型号MUN5111T1/D的Datasheet PDF文件第6页浏览型号MUN5111T1/D的Datasheet PDF文件第7页 
MUN5111T1 Series  
Preferred Devices  
Bias Resistor Transistor  
PNP Silicon Surface Mount Transistor  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a base–emitter  
resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space. The device is housed in the  
SC–70/SOT–323 package which is designed for low power surface  
mount applications.  
http://onsemi.com  
PNP SILICON  
BIAS RESISTOR  
TRANSISTORS  
• Simplifies Circuit Design  
• Reduces Board Space  
• Reduces Component Count  
• The SC–70/SOT–323 package can be soldered using wave or reflow.  
The modified gull–winged leads absorb thermal stress during  
soldering eliminating the possibility of damage to the die.  
PIN 3  
COLLECTOR  
(OUTPUT)  
PIN 1  
BASE  
(INPUT)  
R
R
1
2
PIN 2  
EMITTER  
(GROUND)  
• Available in 8 mm embossed tape and reel  
Use the Device Number to order the 7 inch/3000 unit reel.  
Replace “T1” with “T3” in the Device Number to order  
the 13 inch/10,000 unit reel.  
3
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
1
2
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
SC–70/SOT–323  
CASE 419  
V
CBO  
CEO  
V
50  
Vdc  
STYLE 3  
I
C
100  
mAdc  
THERMAL CHARACTERISTICS  
Characteristic  
MARKING DIAGRAM  
Symbol  
Max  
Unit  
Total Device Dissipation  
P
202 (Note 1.)  
310 (Note 2.)  
1.6 (Note 1.)  
2.5 (Note 2.)  
mW  
D
6x  
M
T = 25°C  
A
Derate above 25°C  
°C/W  
°C/W  
°C/W  
°C  
6x = Specific Device Code  
= (See Marking Table)  
M = Date Code  
Thermal Resistance –  
Junction-to-Ambient  
R
618 (Note 1.)  
403 (Note 2.)  
θ
JA  
JL  
x
Thermal Resistance –  
Junction-to-Lead  
R
280 (Note 1.)  
332 (Note 2.)  
θ
Junction and Storage  
Temperature Range  
T , T  
J
–55 to +150  
stg  
DEVICE MARKING INFORMATION  
See specific marking information in the device marking table  
on page 2 of this data sheet.  
1. FR–4 @ Minimum Pad  
2. FR–4 @ 1.0 x 1.0 inch Pad  
Preferred devices are recommended choices for future use  
and best overall value.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
January, 2001 – Rev. 4  
MUN5111T1/D  
1234567...16

中文翻译

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