MUN2211T1 Series
Preferred Devices
Bias Resistor Transistors
NPN Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The BRT (Bias Resistor
Transistor) contains a single transistor with a monolithic bias network
consisting of two resistors; a series base resistor and a base-emitter
resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space. The device is housed in the
SC-59 package which is designed for low power surface
mount applications.
http://onsemi.com
NPN SILICON
BIAS RESISTOR
TRANSISTORS
PIN 3
COLLECTOR
(OUTPUT)
Features
PIN 2
BASE
(INPUT)
•ꢀSimplifies Circuit Design
•ꢀReduces Board Space
R
R
1
2
•ꢀReduces Component Count
•ꢀMoisture Sensitivity Level: 1
PIN 1
EMITTER
(GROUND)
•ꢀESD Rating - Human Body Model: Class 1
- Machine Model: Class B
•ꢀThe SC-59 Package can be Soldered Using Wave or Reflow
•ꢀThe Modified Gull-Winged Leads Absorb Thermal Stress During
Soldering Eliminating the Possibility of Damage to the Die
•ꢀPb-Free Packages are Available
3
SC-59
CASE 318D
STYLE 1
2
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
MARKING DIAGRAM
Rating
Collector‐Base Voltage
Collector‐Emitter Voltage
Collector Current
Symbol
Value
50
Unit
Vdc
V
CBO
V
CEO
50
Vdc
8xꢀMꢀG
G
I
C
100
mAdc
1
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
8x = Device Code (Refer to page 2)
= Date Code*
Total Device Dissipation
T = 25°C
Derate above 25°C
P
230 (Note 1)
338 (Note 2)
1.8 (Note 1)
2.7 (Note 2)
mW
D
M
A
G = Pb-Free Package
(Note: Microdot may be in either location)
°C/W
°C/W
°C/W
°C
*Date Code orientation may vary depending
upon manufacturing location.
Thermal Resistance, Junction‐to‐Ambient
R
540 (Note 1)
370 (Note 2)
q
JA
Thermal Resistance, Junction‐to‐Lead
R
264 (Note 1)
287 (Note 2)
q
JL
ORDERING INFORMATION
See detailed ordering and shipping information in the table on
page 2 of this data sheet.
Junction and Storage Temperature
Range
T , T
J
-ā55 to +150
stg
DEVICE MARKING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR-4 @ Minimum Pad.
See specific marking information in the Device Marking and
Resistor Values table on page 2 of this data sheet.
Preferred devices are recommended choices for future use
2. FR-4 @ 1.0 x 1.0 inch Pad.
and best overall value.
©ꢀ Semiconductor Components Industries, LLC, 2007
July, 2007 - Rev. 13
1
Publication Order Number:
MUN2211T1/D