Datasheet > MTP4835L3

MTP4835L3

更新时间： 2024-02-03 16:24:30

品牌	Logo	应用领域
全宇昕 - CYSTEKEC		/
页数	文件大小	规格书
8页	342K
描述
P-Channel Logic Level Enhancement Mode Power MOSFET

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数据手册

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MTP4835L3 数据手册

Spec. No. : C830L3

Issued Date : 2013.02.01

Revised Date :

CYStech Electronics Corp.

Page No. : 1/8

P-Channel Logic Level Enhancement Mode Power MOSFET

MTP4835L3

BVDSS

-30V

-10A

21mΩ (typ)

28mΩ (typ)

RDSON@VGS=-10V, ID=-10A

RDSON@VGS=-5V, ID=-7A

Features

• Low Gate Charge

• Simple Drive Requirement

• Pb-free lead plating & Halogen-free package

Equivalent Circuit

Outline

SOT-223

MTP4835L3

G：Gate D：Drain

S：Source

Absolute Maximum Ratings (TC=25°C, unless otherwise noted)

Parameter

Symbol

Limits

Unit

Drain-Source Voltage

Gate-Source Voltage

VDS

-30

±25

-13

-9.2

-10

-8.4

-40

-10

VGS

Continuous Drain Current @ VGS=-10V, TC=25°C

Continuous Drain Current @ VGS=-10V, TC=100°C

Continuous Drain Current @ VGS=-10V, TA=25°C

Continuous Drain Current @ VGS=-10V, TA=70°C

Pulsed Drain Current *1

IDM

IAS

Avalanche Current

Avalanche Energy @ L=0.1mH, ID=-10A, RG=25Ω

Repetitive Avalanche Energy @ L=0.05mH *2

Total Power Dissipation @TA=25℃

EAS

EAR

2.5

3.3

1.65

Total Power Dissipation @TA=100℃

Operating Junction and Storage Temperature Range

Tj, Tstg

-55~+175

°C

MTP4835L3

CYStek Product Specification

12 3 4 5 6 7 8

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