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MTC36F204WS1PC48B PDF预览

MTC36F204WS1PC48B

更新时间: 2024-11-06 17:01:35
品牌 Logo 应用领域
镁光 - MICRON PC
页数 文件大小 规格书
9页 393K
描述
MTC36F204WS1PC – 96GB – 24Gb Die Revision B

MTC36F204WS1PC48B 数据手册

 浏览型号MTC36F204WS1PC48B的Datasheet PDF文件第2页浏览型号MTC36F204WS1PC48B的Datasheet PDF文件第3页浏览型号MTC36F204WS1PC48B的Datasheet PDF文件第4页浏览型号MTC36F204WS1PC48B的Datasheet PDF文件第5页浏览型号MTC36F204WS1PC48B的Datasheet PDF文件第6页浏览型号MTC36F204WS1PC48B的Datasheet PDF文件第7页 
96GB (x72, ECC, DR) 288-Pin DDR5 RDIMM  
Features  
DDR5 SDRAM RDIMM Addendum  
MTC36F204WS1PC – 96GB  
24Gb Die Revision B  
Figure 1: 288-Pin DDR5 RDIMM (R/C-B0)  
Features  
Information provided here is in addition to or super-  
sedes information provided in the Micron DDR5  
RDIMM Core data sheet.  
U1  
U2  
U3  
U4  
U7  
U8  
U9  
U10  
U23  
U11  
U13 U14 U15 U16  
U17  
U18 U19 U20 U21  
DDR5 functionality and operations supported as  
U22  
U12  
defined in the component data sheet  
Sensitive parts:  
Primary side  
Features and specifications defined in the Micron  
U29  
DDR5 RDIMM core data sheet  
U24 U25 U26 U27  
U30  
U32 U33 U34 U35  
288-pin, DDR5 registered dual in-line memory  
U36  
U37 U38 U39 U40  
U41 U42 U43 U44  
U45  
module (DDR5 RDIMM)  
Fast data transfer rate: PC5-4800, PC5-5600, PC5-6400  
96GB (12Gig x 72)  
Secondary side  
Dual-rank  
Figure 2: 288-Pin DDR5 RDIMM (R/C-B1)  
32 internal banks; 8 groups of 4 banks each  
In Development  
Options  
Marking  
Operating temperature  
Commercial (0°C TOPER 95°C)  
Frequency/CAS latency  
C
48B  
56B  
64B  
0.416ns @ CL = 40 (DDR5-4800)  
0.357ns @ CL = 46 (DDR5-5600)  
0.312ns @ CL = 52 (DDR5-6400)  
Table 1: Addressing  
Parameter  
96GB  
Row address1  
96K (R0-R16)2  
2K (C0-C10)  
Column address1  
Device bank group address1  
8 (BG0-BG2)  
4 (BA0-BA1)  
Device bank address per bank group1  
Device configuration  
24Gb (6Gb x 4), 32 banks  
2 (CS0_n, CS1_n)  
Module rank address  
Notes: 1. These parameters represent the logical address state of the CA bus for different commands. Refer to the command  
truth table in the component data sheet.  
2. For non-binary densities, a quarter of the row address space is invalid. When the MSB address bit is HIGH, the MSB-1  
address shall be LOW.  
CCM005-802248454-57  
mtc36f204ws1pc_drx4_rdimm_dierevB.pdf - Rev. C 01/2023  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
1
© 2022 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are subject to change by Micron without notice.  

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