288-Pin DDR5 RDIMM Core
Product Description
DDR5 SDRAM RDIMM Core
Product Description
Features
• DDR5 functionality and operations supported as de-
fined in the component data sheet
• 287/288-pin RDIMM
• Supports ECC error detection and correction
• On-DIMM SPD EEPROM with Hub function and inte-
grated temperature sensor (TS)
• Two on-DIMM discrete TS5 temperature sensors
• On-DIMM power management integrated circuit
(PMIC)
• Sideband access with I3C-basic/I2C support
• Two independent I/O sub channels for increased
bandwidth
This specification defines the electrical and mechanical
requirements for 287-pin and 288-pin, 1.1V (VDD
)
double data rate, synchronous DRAM, registered dual
in-line memory modules (DDR5 SDRAM RDIMMs).
These DDR5 RDIMMs are intended for use as main
memory when installed in servers. Some specifications
are part number-specific; refer to the module data sheet
addendum of the specific Micron part number (MPN)
for the complete specification.
• DDR command/address bus to RCD
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated clock, control and command/address
bus
Figure 1: DDR5 LRDIMM/RDIMM Functional Block Diagram
TS0
TS1
Channel A
Channel B
Rank 0 (Front Side)
CK_AA
CS_0AB
CK_BA
CS_0BB
CA_0A[13:0]BB
CA_0A[13:0]AB
CS_1BB
CK_BB
CS_1AB
CK_AB
DLBD_A
DLBS_A
DLBD_B
DLBS_B
RESET_A
ERROR_A
RESET_B
ERROR_B
RCD
Rank 1 (Back Side)
CK_AC
CK_BC
CS_1AA
CS_1BA
PMIC
CA_0A[13:0]AA
CA_0A[13:0]BA
CS_0AA
CK_AD
CS_0BA
CK_BD
SPD
(HUB)
BCK_A
BCK_B
BCOM_A
BCOM_B
LRDIMM only
2 Chip selects
7 CA (DDR)
1 Parity
2 Chip selects
7 CA (DDR)
1 Parity
DQ[31:0]_A, CB[7:0]_A, DQS[7:0]_A
DQ[31:0]_B, CB[7:0]_B, DQS[7:0]_B
I3C
ALERT
CLOCK, RESET
Note: 1. The above illustrates a dual-rank x80 LRDIMM/RDIMM with DRAM, PMIC, RCD, SPD, temp sensors and data buffers.
CCM005-802248454-6
ddr5_rdimm_core.pdf - Rev. G 05/2023 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.